UCS2112 datasheet(34/64 Pages) MICROCHIP

34 / 64 page

UCS2112

DS20005424B-page 34

 2015 Microchip Technology Inc.

8.0

SYSTEM MANAGEMENT BUS

PROTOCOL

In SMBus mode, the UCS2112 communicates with a

host controller, such as an Microchip PIC® microcon-

troller or hub, through the SMBus. The SMBus is a

two-wire serial communication protocol between a

computer host and its peripheral devices. A detailed

timing diagram is shown in Figure 1-1. Stretching of

the SMCLK signal is supported; however, the

UCS2112 will not stretch the clock signal.

8.1

SMBus Start Bit

The SMBus Start bit is defined as a transition of the

SMBus Data line from a logic ‘1’ state to a logic ‘0’

state while the SMBus Clock line is in a logic ‘1’ state.

8.2

SMBus Address and RD/WR Bit

The SMBus Address Byte consists of the 7-bit client

address followed by the RD/WR indicator bit. If this

RD/WR bit is a logic ‘0’, the SMBus Host is writing

data to the client device. If this RD/WR bit is a logic ‘1’,

the SMBus Host is reading data from the client device.

The UCS2112 with the order code UCS2112-1-V/G4

has the SMBus address 57h - 1010_111(r/w).

Customers should contact their distributor, representa-

tives or field application engineer (FAE) for additional

SMBus addresses. Local sales offices are also avail-

able to help customers. A list of sales offices and loca-

tions is included in the back of this document.

8.3

SMBus Data Bytes

All SMBus Data bytes are sent most significant bit first

and composed of 8 bits of information.

8.4

SMBus ACK and NACK Bits

The SMBus client will acknowledge all data bytes that

it receives. This is done by the client device pulling the

SMBus Data line low after the 8th bit of each byte that

is transmitted. This applies to both the Write Byte and

Block Write protocols.

The Host will NACK (not acknowledge) the last data byte

to be received from the client by holding the SMBus data

line high after the 8th data bit has been sent. For the

Block Read protocol, the Host will ACK (acknowledge)

each data byte that it receives except the last data byte.

8.5

SMBus Stop Bit

The SMBus Stop bit is defined as a transition of the

SMBus Data line from a logic ‘0’ state to a logic ‘1’

state while the SMBus clock line is in a logic ‘1’ state.

When the UCS2112 detects an SMBus Stop bit and it

has been communicating with the SMBus protocol, it

will reset its client interface and prepare to receive fur-

ther communications.

8.6

SMBus Time-out

The UCS2112 includes an SMBus time-out feature. If

the clock is held at logic ‘0’ for tTIMEOUT, the device

can time out and reset the SMBus interface. The

SMBus interface can also reset if both the clock and

data lines are held at a logic ‘1’ for tIDLE_RESET. Com-

munication is restored with a start condition.

The time-out function defaults to disabled. It can be

enabled by clearing the DIS_TO bit in the General

Configuration 3 register (see Register 9-9).

8.7

SMBus and I2C Compliance

The major difference between SMBus and I2C devices

is highlighted here. For complete compliance informa-

tion, refer to the SMBus 2.0 specification and Applica-

tion Note 14.0.

• UCS2112 supports I2C fast mode at 400 kHz. This

covers the SMBus maximum time of 100 kHz.

• The minimum frequency for SMBus communica-

tions is 10 kHz.

• The client protocol will reset if the clock is held low

longer than 30 ms. This time out functionality is

disabled by default in the UCS2112 and can be

enabled by clearing the DIS_TO bit. I2C does not

have a time out.

• Except when operating in Sleep, the client proto-

col will reset if both the clock and the data line are

logic ‘1’ for longer than 200 µs (idle condition).

This function is disabled by default in the

UCS2112 and can be enabled by clearing the

DIS_TO bit. I2C does not have an idle condition.

•I2C devices do not support the Alert Response

Address functionality (which is optional for SMBus).

•I2C devices support block read and write differ-

ently. I2C protocol allows for unlimited number of

bytes to be sent in either direction. The SMBus

protocol requires that an additional data byte indi-

cating number of bytes to read/write is transmit-

ted. The UCS2112 supports I2C formatting only.

8.8

SMBus Protocols

The UCS2112 is SMBus 2.0-compatible and supports

Send Byte, Read Byte, Block Read, Receive Byte as

valid protocols as shown below. The UCS2112 also

supports the I2C block read and block write protocols.

The device supports Write Byte, Read Byte, and Block

Read/Block Write. All of the below protocols use the

convention in Table 8-1.

TABLE 8-1:

SMBUS PROTOCOL

Data Sent to Device

Data Sent to the Host

Data sent

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