UCS2112 datasheet(23/64 Pages) MICROCHIP

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DS20005424B-page 23

UCS2112

5.3

Supply Voltages

5.3.1

VDD SUPPLY VOLTAGE

The UCS2112 requires 4.5V to 5.5V present on the

VDD pin for core device functionality. Core device func-

tionality consists of maintaining register states,

wake-up upon SMBus/I2C query and Attach Detection.

5.3.2

BACK-VOLTAGE DETECTION

The back drive detector is functional in all power states

(Sleep, Detect, and Active).

When in Sleep, the UCS2112 will enter the Error state

from Sleep if a Back Drive condition was detected.

Whenever the following condition is true for either port,

the port power switch will be disabled, the VBUS bypass

switch will be disabled and a back-voltage event will be

flagged. This will cause the UCS2112 to enter the Error

power state (see Section 5.1.5 “Error State Opera-

tion”

5.3.3

BACK-DRIVE CURRENT

PROTECTION

If a portable device is attached that is self-powered, it

may drive the VBUS port to its power supply voltage

level; however, the UCS2112 is designed such that

leakage current from the VBUS pins to the VDD and/or

the VS pin shall not exceed IBD_1 (if the VDD and/or VS

voltage is zero) or IBD_2 (if the VDD and/or VS voltage

exceeds VDD_TH).

5.3.4

UNDERVOLTAGE LOCKOUT ON VS

The UCS2112 requires a minimum voltage (VS_UVLO)

be present on the VS pin for Active power state.

5.3.5

OVERVOLTAGE DETECTION AND

LOCKOUT ON VS/VDD

The UCS2112 port power switch will be disabled if the

voltage on the VS pin exceeds a voltage (VS_OV) for

longer than the specified time (tMASK). This will cause

the device to enter the Error state.

5.3.6

PWR_EN1 AND PWR_EN2 INPUT

The PWR_EN control affects the power state and

enables the port power switch to be turned on if condi-

tions are met (see Table 5-2). The port power switch

cannot be closed if PWR_EN is disabled. However, if

PWR_EN is enabled, the port power switch is not nec-

essarily closed (see Section 5.1.4 “Active State

Operation”

). In SMBus mode, the PWR_EN1 and

PWR_EN2 pins states will be ignored by the UCS2112

if the PIN_IGN configuration bit is set; otherwise, the

PWR_EN1S and PWR_EN2S configuration bits are

checked along with the pins.

27 k



Active-High

2.67

2.67+2.67

SMBUS

33 k



Active-High

3.2

3.2+3.2

SMBUS

47 k



Active-Low

0.53

0.53+0.53

Stand-Alone

56 k



Active-Low

0.96

0.96+0.96

Stand-Alone

68 k



Active-Low

1.07

1.07+1.07

Stand-Alone

82 k



Active-Low

1.28

1.28+1.28

Stand-Alone

100 k



Active-Low

1.6

1.6+1.6

Stand-Alone

120 k



Active-Low

2.13

2.13+2.13

Stand-Alone

150 k



Active-Low

2.67

2.67+2.67

Stand-Alone

VDD

Active-Low

3.2

3.2+3.2

Stand-Alone

Note 1:

The total maximum current depends on power dissipation characteristics of the design (see Table 1-1)

TABLE 5-3:

COMMUNICATION DECODE (CONTINUED)

COMM_ILIM Pulldown

Resistor (±1%)

PWR_EN1 and

PWR_EN2 Polarity

ILIM (A)

Total ILIM (A)

(Note 1)

Communication

Mode

Note:

The VBUS voltage exceeds the VS and/or

the VDD pin voltage by VBV_TH and the

port power switch is closed. The port

power switch will be opened immediately.

If the condition lasts for longer than tMASK,

then the UCS2112 will enter the Error

state. Otherwise, the port power switch

will be turned on as soon as the condition

is removed.

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