UCS2112 datasheet(40/64 Pages) MICROCHIP

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UCS2112

DS20005424B-page 40

 2015 Microchip Technology Inc.

INTERRUPT STATUS 1 REGISTER (ADDRESS 03H)

R/W-0

R/C-0

ERR1

DISCH_ERR1

RESET

KEEP_OUT1

TSD

OV_VOLT

BACK_V1

OV_LIM1

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit

C = Clear on Read

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

ERR1:

Error Port 1 - Indicates that an error was detected on the VBUS1 pin and the device has entered

the Error state. Writing this bit to ‘0’ will clear the Error state and allows the device to be returned to the

Active state. When written to ‘0’, all error conditions are checked. If all error conditions have been

removed, the UCS2112 returns to the Active state. This bit is set automatically by the UCS2112 when

the Error state is entered. If any other bit is set in the Interrupt Status register (03h), the device will not

leave the Error state.

This bit is cleared automatically by the UCS2112 if the Auto-recovery fault handling functionality is active

and no error conditions are detected. Likewise, this bit is cleared when the PWR_EN1 control is disabled

(Note 1).

= Port 1 in Error State.

= Port 1 in Active State (no errors detected).

bit 6

DISCH_ERR1:

Discharge Error Port 1 - indicates the device was unable to discharge Port1. This bit will

be cleared when read if the error condition has been removed or if the ERR bit is cleared. This bit will

cause the ALERT#1 pin to be asserted and the device to enter the Error state.

= UCS2112 was unable to Discharge VBUS1.

=No VBUS1 discharge error.

bit 5

RESET:

Indicates that the UCS2112 has just been reset and should be re-programmed. This bit will be

set at power-up. This bit is cleared when read or when the PWR_EN control is toggled. The ALERT#

pins are not asserted when this bit is set. This data is retained in the Sleep state.

= UCS2112 has just been reset.

= Reset did not occur.

bit 4

KEEP_OUT1:

Port 1 Minimum Keep-out region - Indicates that the V-I output on the VBUS1 pin has

dropped below VBUS_MIN. This bit will be cleared when read if the error condition has been removed or

if the ERR1 bit is cleared. This bit will cause the ALERT#1 pin to be asserted and the device to enter the

Error state.

=VBUS1 < VBUS_MIN

=VBUS1 > VBUS_MIN

bit 3

TSD:

Thermal Shutdown - Indicates that the internal temperature has exceeded TTSD threshold and the

device has entered the Error state. This bit will be cleared when read if the error condition has been

removed or if the ERR1 bit is cleared. This bit will cause the ALERT#1and ALERT#2 pins to be asserted

and the device to enter the Error state.

= Thermal Shutdown Temperature reached.

= Internal temperature < TTSD

bit 2

OV_VOLT:

VS Overvoltage Indicates that the VS voltage has exceeded the VS_OV threshold, and the

device has entered the Error state. This bit will be cleared when read if the error condition has been

removed or if the ERR1 bit is cleared. This bit will cause the ALERT#1 and ALERT#2 pins to be asserted

and the device to enter the Error state.

=VS > VS_OV

=VS < VS_OV

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