UCS2112 datasheet(42/64 Pages) MICROCHIP

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UCS2112

DS20005424B-page 42

 2015 Microchip Technology Inc.

INTERRUPT STATUS 2 REGISTER (ADDRESS 04H)

R/W-0

R/C-0

R-0

R/C-0

U-0

R/C-0

ERR2

DISCH_ERR2

VS_LOW

KEEP_OUT2

TREG

—

BACK_V2

OV_LIM2

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit

C = Clear on Read

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

ERR2:

Error Port 2 - Indicates that an error was detected on the VBUS1 pin and the device has entered

the Error state. Writing this bit to a ‘0’ will clear the Error state and allows the device to be returned to

the Active state. When written to ‘0’, all error conditions are checked. If all error conditions have been

removed, the UCS2112 returns to the Active state. This bit is set automatically by the UCS2112 when

the Error state is entered. If any other bit is set in the Interrupt Status register (04h), the device will not

leave the Error state. This bit is cleared automatically by the UCS2112 if the auto-recovery fault handling

functionality is active and no error conditions are detected. Likewise, this bit is cleared when the

PWR_EN2 control is disabled (Note 1).

= Port 2 in Error State.

= Port 2 in Active State (no errors detected).

bit 6

DISCH_ERR2:

Discharge Error Port 2 - indicates the device was unable to discharge Port2. This bit will

be cleared when read if the error condition has been removed or if the ERR bit is cleared. This bit will

cause the ALERT#2 pin to be asserted and the device to enter the Error state.

= Device was unable to Discharge VBUS2.

= No VBUS2 discharge error.

bit 5

VS_LOW:

Indicates that the VS voltage has fallen below the VS_UVLO threshold and both VBUS1 and

VBUS2 port power switches are held off. This bit is cleared automatically when the VS voltage is above

the VS_UVLO threshold.

=VS voltage has fallen below the VS_UVLO.

=VS voltage is above VS_UVLO.

bit 4

KEEP_OUT2:

Port 2 Minimum Keep-out region - Indicates that the V-I output on the VBUS2 pin has

dropped below VBUS_MIN. This bit will be cleared when read if the error condition has been removed or

if the ERR2 bit is cleared. This bit will cause the ALERT#2 pin to be asserted and the device to enter the

Error state.

=VBUS2 < VBUS_MIN

=VBUS2 > VBUS_MIN

bit 3

TREG:

Thermal Regulation - Indicates that the internal temperature has exceeded TREG and that the

current limit has been reduced. This bit is cleared when read and will not cause the ALERT#1 and

ALERT#2 pins to be asserted unless the ALERT_LINK bit is set.

= Internal temperature > TREG

= Internal temperature < TREG

bit 2

Unimplemented:

Read as '0'

bit 1

BACK_V2:

Back-Bias Voltage Port 2 - Indicates that the VBUS2 voltage has exceeded the VS or VDD

voltages by more than 150 mV. This bit will be cleared when read if the error condition has been removed

or if the ERR2 bit is cleared. This bit will cause the ALERT#2 pin to be asserted and the device to enter

the Error state.

=VBUS2 > VS, or VBUS2 > VDD by more than 150 mV.

=VBUS2 voltage has not exceeded the VS and VDD voltages by more than 150 mV.

bit 0

OV_LIM2:

Overcurrent Limit Port 2 - Indicates that the IBUS current has exceeded both the ILIM threshold

and the IBUS_R2MIN threshold settings for VBUS2. This bit will be cleared when read if the error condition

has been removed or if the ERR2 bit is cleared. This bit will cause the ALERT#2 pin to be asserted and

the device to enter the Error state.

= Current Limit for Port 2 exceeded

= Current Limit for Port 2 not exceeded.

Note

Note that the ERR2 bit does not necessarily reflect the ALERT#2 pin status. The ALERT#2 pin may be cleared or

asserted without the ERR2 bit changing states.

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