UCS2112 datasheet(33/64 Pages) MICROCHIP

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DS20005424B-page 33

UCS2112

7.6

Fault Handling Mechanism

The UCS2112 has two modes for handling faults:

• Latch (latch-upon-fault)

• Auto-recovery (automatically attempt to restore

the Active power state after a fault occurs).

If the SMBus is actively utilized, Auto-Recovery Fault

Handling is the default error handler as determined by

the LATCH_SET bit. Faults include overcurrent,

overvoltage (on VS), undervoltage (on VBUS),

back-voltage (VBUS to VS or VBUS to VDD), discharge

error, and maximum allowable internal die temperature

(TTSD) exceeded. Faults do not include keep-out

violations except VBUS_MIN.

7.6.1

AUTO-RECOVERY FAULT

HANDLING

When the LATCH_SET bit is low, Auto-Recovery Fault

Handling is used. When an error condition is detected,

the UCS2112 will immediately enter the Error state

and assert the ALERT# pin. Independently from the

host controller, the UCS2112 will wait a preset time

(tCYCLE), check error conditions (tTST), and restore

Active operation if the error condition(s) no longer

exist. If all other conditions that may cause the

ALERT# pin to be asserted have been removed, the

ALERT#

will

released.

Short-Circuit

Auto-Recovery example in Figure 7-6.

FIGURE 7-6:

Error Recovery.

7.6.2

LATCHED FAULT HANDLING

When the LATCH_SET bit is high, latch fault handling

is used. When an error condition is detected, the

UCS2112 will enter the Error power state and assert

the ALERT# (1 or 2) pin. Upon command from the host

controller (by toggling the PWR_EN (1, or 2) pin con-

trol from enabled to disabled or by clearing the ERR bit

via SMBus), the UCS2112 will check error conditions

once and restore Active operation if error conditions

no longer exist. If an error condition still exists, the

host controller is required to issue the command again

to check error conditions.

If the ALERT# pin is asserted and the interrupt status

registers (addresses 03h or 04h) are not read, the cor-

responding ALERT# pin remains asserted until the

corresponding PWR_EN pin is toggled.

If the ALERT# pin is asserted and the interrupt status

registers are read, the ALERT# pin will de-assert, but

the UCS will remain in error state until the ERR bit is

cleared via SMBus or the PWR_EN pin is toggled.

tTST

VBUS

IBUS

SHORT

applied.

ITEST

tDISCHARGE

ITEST

VTEST

Short Detected. VBUS

discharged. Enter

Error state.

Check short

condition. Short

still present.

Return to Error

State.

Wait tCYCLE.

Check short

condition. Short

removed.

Return to

normal

operation.

tCYCLE

tTST

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