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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AT90LS4433-4AI датащи(PDF) 53 Page - ATMEL Corporation |
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AT90LS4433-4AI датащи(HTML) 53 Page - ATMEL Corporation |
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53 / 126 page  53 AT90S/LS4433 1042H–AVR–04/03 UART The AT90S4433 features a full duplex (separate Receive and Transmit Registers) Uni- versal Asynchronous Receiver and Transmitter (UART). The main features are: • Baud Rate Generator Generates any Baud Rate • High Baud Rates at Low XTAL Frequencies • 8 or 9 Bits Data • Noise Filtering • Overrun Detection • Framing Error Detection • False Start Bit Detection • Three Separate Interrupts on TX Complete, TX Data Register Empty, and RX Complete • Multi-processor Communication Mode Data Transmission A block schematic of the UART Transmitter is shown in Figure 40. Figure 40. UART Transmitter Data transmission is initiated by writing the data to be transmitted to the UART I/O Data Register (UDR). Data is transferred from UDR to the Transmit Shift Register when: • A new character has been written to UDR after the stop bit from the previous character has been shifted out. The Shift Register is loaded immediately. • A new character has been written to UDR before the stop bit from the previous character has been shifted out. The Shift Register is loaded when the stop bit of the character currently being transmitted has been shifted out. When data is transferred from UDR to the Shift Register, the UDRE (UART Data Regis- ter Empty) bit in the UART Control and Status Register A, UCSRA, is set. When this bit is set (one), the UART is ready to receive the next character. At the same time as the UART CONTROL AND STAUS REGISTER B (UCSRB) UART CONTROL AND STAUS REGISTER A (UCSRA) |
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