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AT90LS4433-4AI датащи(PDF) 24 Page - ATMEL Corporation |
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AT90LS4433-4AI датащи(HTML) 24 Page - ATMEL Corporation |
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24 / 126 page ![]() 24 AT90S/LS4433 1042H–AVR–04/03 Figure 25. MCU Start-up, RESET Tied to V CC Figure 26. MCU Start-up, RESET Controlled Externally External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a Reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a Reset. When the applied signal reaches the Reset Threshold Voltage (V RST) on its positive edge, the delay timer starts the MCU after the Time-out period (t TOUT) has expired. Figure 27. External Reset during Operation VCC RESET TIME-OUT INTERNAL RESET t TOUT V POT V RST VCC RESET TIME-OUT INTERNAL RESET t TOUT V POT V RST |
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