AT90LS4433-4AI datasheet(31/126 Pages) ATMEL

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AT90S/LS4433

1042H–AVR–04/03

• Bits 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0

The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the

corresponding interrupt mask in the GIMSK are set. The level and edges on the external

INT1 pin that activate the interrupt are defined in Table 7.

The value on the INT1 pin is sampled before detecting edges. If edge or toggle interrupt

is selected, pulses that last longer than one clock period will generate an interrupt.

Shorter pulses are not guaranteed to generate an interrupt. If low-level interrupt is

selected, the low level must be held until the completion of the currently executing

instruction to generate an interrupt.

• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the

corresponding interrupt mask are set. The level and edges on the external INT0 pin that

activate the interrupt are defined in Table 8.

The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt

is selected, pulses that last longer than one clock period will generate an interrupt.

Shorter pulses are not guaranteed to generate an interrupt. If low-level interrupt is

selected, the low level must be held until the completion of the currently executing

instruction to generate an interrupt.

Sleep Modes

To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruc-

tion must be executed. The SM bit in the MCUCR Register selects which sleep mode

(Idle or Power-down) will be activated by the SLEEP instruction. If an enabled interrupt

occurs while the MCU is in a sleep mode, the MCU wakes up, executes the interrupt

routine, and resumes execution from the instruction following SLEEP. The contents of

the Register File and I/O memory are unaltered. If a reset occurs during sleep mode, the

MCU wakes up and executes from the Reset Vector.

Note that if a level-triggered interrupt is used for wake-up from Power-down, the low

level must be held for a time longer than the reset delay Time-out period (t

TOUT). Other-

wise, the device will not wake up.

Table 7. Interrupt 1 Sense Control

ISC11

ISC10

Description

The low level of INT1 generates an interrupt request.

Any logical change on INT1 generates an interrupt request.

The falling edge of INT1 generates an interrupt request.

The rising edge of INT1 generates an interrupt request.

Table 8. Interrupt 0 Sense Control

ISC01

ISC00

Description

The low level of INT0 generates an interrupt request.

Any logical change on INT0 generates an interrupt request.

The falling edge of INT0 generates an interrupt request.

The rising edge of INT0 generates an interrupt request.

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