AT90LS4433-4AI datasheet(29/126 Pages) ATMEL

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AT90S/LS4433

1042H–AVR–04/03

Timer/Counter Interrupt Flag

• Bit 7 – TOV1: Timer/Counter1 Overflow Flag

The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by

hardware when executing the corresponding interrupt handling vector. Alternatively,

TOV1 is cleared by writing a logical “1” to the flag. When the I-bit in SREG and TOIE1

(T im er/Co u n t er1 Ove r flow Inte rrup t En able) an d TO V1 a r e set (o ne) , th e

Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when

Timer/Counter1 advances from $0000.

• Bit 6 – OCF1: Output Compare Flag 1

The OCF1 bit is set (one) when a Compare Match occurs between the Timer/Counter1

and the data in Output Compare Register 1 (OCR1). OCF1 is cleared by hardware when

executing the corresponding interrupt handling vector. Alternatively, OCF1 is cleared by

writing a logical “1” to the flag. When the I-bit in SREG and OCIE1 (Timer/Counter1

Compare Match Interrupt A Enable) and the OCF1 are set (one), the Timer/Counter1

Compare Match Interrupt is executed.

• Bits 5, 4 – Res: Reserved Bits

These bits are reserved bits in the AT90S4433 and always read as zero.

• Bit 3 – ICF1: Input Capture Flag 1

The ICF1 bit is set (one) to flag an Input Capture Event, indicating that the

Timer/Counter1 value has been transferred to the Input Capture Register (ICR1). ICF1

is cleared by hardware when executing the corresponding interrupt handling vector.

Alternatively, ICF1 is cleared by writing a logical “1” to the flag. When the SREG I-bit

and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable) and ICF1 are set (one), the

Timer/Counter1 Capture Interrupt is executed.

• Bit 2 – Res: Reserved Bit

This bit is a reserved bit in the AT90S4433 and always reads as zero.

• Bit 1 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared

by hardware when executing the corresponding interrupt handling vector. Alternatively,

TOV0 is cleared by writing a logical “1” to the flag. When the SREG I-bit and TOIE0

(T im er/Co u n t er0 Ove r flow Inte rrup t En able) an d TO V0 a r e set (o ne) , th e

Timer/Counter0 Overflow Interrupt is executed.

• Bit 0 – Res: Reserved Bit

This bit is a reserved bit in the AT90S4433 and always reads as zero.

Bit

$38 ($58)

TOV1

OCF1

–

ICF1

–

TOV0

–

TIFR

Read/Write

R/W

Initial Value

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