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AT90LS4433-4AI датащи(PDF) 16 Page - ATMEL Corporation |
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AT90LS4433-4AI датащи(HTML) 16 Page - ATMEL Corporation |
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16 / 126 page ![]() 16 AT90S/LS4433 1042H–AVR–04/03 EEPROM Data Memory The AT90S4433 contains 256 bytes of data EEPROM memory. It is organized as a sep- arate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles per location. The access between the EEPROM and the CPU is described on page 53, specifying the EEPROM Address Reg- isters, the EEPROM Data Register and the EEPROM Control Register. For the SPI Data downloading, see page 93 for a detailed description. The EEPROM Data memory is In-System Programmable through the SPI port. Please refer to the “EEPROM Read/Write Access” section on page 45 for a thorough description of EEPROM access. Memory Access Times and Instruction Execution Timing This section describes the general access timing concepts for instruction execution and internal memory access. The AVR CPU is driven by the System Clock Ø, directly generated from the external clock crystal for the chip. No internal clock division is used. Figure 21 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks and functions per power unit. Figure 21. The Parallel Instruction Fetches and Instruction Executions Figure 22 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed and the result is stored back to the destination register. Figure 22. Single Cycle ALU Operation The internal data SRAM access is performed in two System Clock cycles as described in Figure 23. System Clock Ø 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch T1 T2 T3 T4 System Clock Ø Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back T1 T2 T3 T4 |
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