AT90LS4433-4AI datasheet(73/126 Pages) ATMEL

73 / 126 page

AT90S/LS4433

1042H–AVR–04/03

The Port B Input Pins address (PINB) is not a register; this address enables access to

the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is

read, and when reading PINB, the logical values present on the pins are read.

Port B as General Digital I/O

All six pins in Port B have equal functionality when used as digital I/O pins.

PBn, general I/O pin: The DDBn bit in the DDRB Register selects the direction of this

pin. If DDBn is set (one), PBn is configured as an output pin. If DDBn is cleared (zero),

PBn is configured as an input pin. If PORTBn is set (one) when the pin is configured as

an input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, the

PORTBn has to be cleared (zero) or the pin has to be configured as an output pin. The

port pins are tri-stated when a reset condition becomes active, even if the clock is not

running.

Note:

1. n: 5..0, pin number.

Alternate Functions of Port B

The alternate pin configuration is as follows:

• SCK – Port B, Bit 5

SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is

enabled as a Slave, this pin is configured as an input, regardless of the setting of DDB5.

When the SPI is enabled as a Master, the data direction of this pin is controlled by

DDB5. When the pin is forced to be an input, the pull-up can still be controlled by the

PORTB5 bit. See the description of the SPI port for further details.

• MISO – Port B, Bit 4

MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is

enabled as a Master, this pin is configured as an input, regardless of the setting of

DDB4. When the SPI is enabled as a Slave, the data direction of this pin is controlled by

DDB4. When the pin is forced to be an input, the pull-up can still be controlled by the

PORTB4 bit. See the description of the SPI port for further details.

• MOSI – Port B, Bit 3

MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is

enabled as a Slave, this pin is configured as an input, regardless of the setting of DDB3.

When the SPI is enabled as a Master, the data direction of this pin is controlled by

DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the

PORTB3 bit. See the description of the SPI port for further details.

•SS – Port B, Bit 2

SS: Slave Port Select input. When the SPI is enabled as a Slave, this pin is configured

as an input, regardless of the setting of DDB2. As a Slave, the SPI is activated when this

pin is driven low. When the SPI is enabled as a Master, the data direction of this pin is

Table 24. DDBn Effects on Port B Pins

(1)

DDBn

PORTBn

I/O

Pull-up

Comment

Input

Tri-state (high-Z)

Input

Yes

PBn will source current if ext. pulled low.

Output

Push-pull Zero Output

Output

Push-pull One Output

AT90LS4433-4AI датащи(PDF) 73 Page - ATMEL Corporation

AT90LS4433-4AI датащи(HTML) 73 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL