AT90LS4433-4AI datasheet(43/126 Pages) ATMEL

43 / 126 page

AT90S/LS4433

1042H–AVR–04/03

Watchdog Timer

The Watchdog Timer is clocked from a separate On-chip Oscillator. By controlling the

Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in

Table 6. See characterization data for typical values at other V

CC levels. The WDR

(Watchdog Reset) instruction resets the Watchdog Timer. Eight different clock cycle

periods can be selected to determine the reset period. If the reset period expires without

another Watchdog Reset, the AT90S4433 resets and executes from the Reset vector.

For timing details on the Watchdog Reset, refer to page 25.

To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be

followed when the Watchdog is disabled. Refer to the description of the Watchdog Timer

Control Register for details.

Figure 35. Watchdog Timer

Watchdog Timer Control

• Bits 7..5 – Res: Reserved Bits

These bits are reserved bits in the AT90S4433 and will always read as zero.

• Bit 4 – WDTOE: Watchdog Turn-off Enable

This bit must be set (one) when the WDE bit is cleared. Otherwise, the Watchdog will

not be disabled. Once set, hardware will clear this bit to zero after four clock cycles.

Refer to the description of the WDE bit for a Watchdog disable procedure.

• Bit 3 – WDE: Watchdog Enable

When the WDE is set (one), the Watchdog Timer is enabled; if the WDE is cleared

(zero), the Watchdog Timer function is disabled. WDE can only be cleared if the

WDTOE bit is set (one). To disable an enabled Watchdog Timer, the following proce-

dure must be followed:

In the same operation, write a logical “1” to WDTOE and WDE. A logical “1” must

be written to WDE even though it is set to one before the disable operation

starts.

Within the next four clock cycles, write a logical “0” to WDE. This disables the

Watchdog.

Bit

765

321

$21 ($41)

–

WDTOE

WDE

WDP2

WDP1

WDP0

WDTCR

Read/Write

R/W

Initial Value

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