AT90LS4433-4AI datasheet(26/126 Pages) ATMEL

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AT90S/LS4433

1042H–AVR–04/03

MCU Status Register –

MCUSR

The MCU Status Register provides information on which reset source caused an MCU

Reset.

• Bits 7..4 – Res: Reserved Bits

These bits are reserved bits in the AT90S4433 and always read as zero.

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is cleared by a Power-On Reset, or by

writing a logical “0” to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is cleared by a Power-on Reset, or by

writing a logical “0” to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is cleared by a Power-on Reset, or by

writing a logical “0” to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is cleared only by writing a logical “0”

to the flag.

To make use of the Reset Flags to identify a reset condition, the user should read and

then clear the MCUSR as early as possible in the program. If the register is cleared

before another reset occurs, the source of the reset can be found by examining the

Reset Flags.

Interrupt Handling

The AT90S4433 has two 8-bit Interrupt Mask Control Registers; GIMSK (General Inter-

rupt Mask) Register and TIMSK (Timer/Counter Interrupt Mask) Register.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter-

rupts are disabled. The user software can set (one) the I-bit to enable nested interrupts.

The I-bit is set (one) when a Return from Interrupt instruction (RETI) is executed.

When the Program Counter is vectored to the actual Interrupt Vector in order to execute

the interrupt handling routine, hardware clears the corresponding flag that generated the

interrupt. Some of the interrupt flags can also be cleared by writing a logical “1” to the

flag bit position(s) to be cleared.

If an interrupt condition occurs when the corresponding interrupt enable bit is cleared

(zero), the Interrupt Flag will be set and remembered until the interrupt is enabled or the

flag is cleared by software.

If one or more interrupt conditions occur when the Global Interrupt Enable bit is cleared

(zero), the corresponding Interrupt Flag(s) will be set and remembered until the Global

Interrupt Enable bit is set (one), and will be executed by order of priority.

Note that external level interrupt does not have a flag and will only be remembered for

as long as the interrupt condition is active.

Bit

765

432

$34 ($54)

–

WDRF

BORF

EXTRF

PORF

MCUSR

Read/Write

R/W

Initial Value

See Bit Description

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