AT90LS4433-4AI datasheet(40/126 Pages) ATMEL

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AT90S/LS4433

1042H–AVR–04/03

the TEMP Register. Consequently, the Low Byte TCNT1L must be accessed first for a

full 16-bit register read operation.

The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read

and write access. If Timer/Counter1 is written to and a clock source is selected, the

Timer/Counter1 continues counting in the timer clock cycle after it is preset with the writ-

ten value.

Timer/Counter1 Output

Compare Register – OCR1H

and OCR1L

The Output Compare Register is a 16-bit read/write register.

The Timer/Counter1 Output Compare Register contains the data to be continuously

compared with Timer/Counter1. Actions on compare matches are specified in the

Timer/Counter1 Control and Status Register.

Since the Output Compare Register (OCR1) is a 16-bit register, a temporary register

TEMP is used when OCR1 is written to ensure that both bytes are updated simulta-

neously. When the CPU writes the High Byte, OCR1H, the data is temporarily stored in

the TEMP Register. When the CPU writes the Low Byte, OCR1L, the TEMP Register is

simultaneously written to OCR1H. Consequently, the High Byte OCR1H must be written

first for a full 16-bit register write operation.

The TEMP Register is also used when accessing TCNT1 and ICR1. If the main program

and interrupt routines perform access to registers using TEMP, interrupts must be dis-

abled during access from the main program.

Bit

15141312

$2B ($4B)

MSB

OCR1H

$2A ($4A)

LSB

OCR1L

543

210

Read/Write

R/W

R/WR/W

Initial Value

000

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