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HM17CM256 датащи(PDF) 73 Page - Hynix Semiconductor |
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HM17CM256 датащи(HTML) 73 Page - Hynix Semiconductor |
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73 / 111 page ![]() HM17CM256 - 73 - (34-27) Line inversion start address set CS RS RD WR RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 0 1 0 1 0 1 0 0 LS3 LS2 LS1 LS0 ( reset :{LS3~LS0}=0H, read address :4H) CS RS RD WR RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 0 1 0 1 0 1 0 1 * LS6 LS5 LS4 ( reset :{LS6~LS4}=0H, read address :5H) * : “Don’t care” When the start address of negative display is set on, it is set by this command. The lower 4 bits of address should be set first and then upper 3 bits are set later. The possible range is LS=00H~4FH . The other values are forbidden. Please set the value under the condition, LS ≤LE. (34-28) Line inversion end address set CS RS RD WR RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 0 1 0 1 0 1 1 0 LE3 LE2 LE1 LE0 ( reset :{LE3~LE0}=0H, read address :6H) CS RS RD WR RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 0 1 0 1 0 1 1 1 * LE6 LE5 LE4 ( reset :{LE6~LE4}=0H, read address :7H) * : “Don’t care” When the end address of negative display is set on, it is set by this command. The lower 4 bits of address should be set first and then upper 3 bits are set later. The possible range is LS=00H~4FH . The other values are forbidden. Please set the value under the condition, LS ≤LE. (34-29) Line inversion control CS RS RD WR RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 0 1 0 1 1 0 0 0 * * BT LREV ( reset :{PSC, BT, LREV}=0H, read address :8H) * : “Don’t care” Setting the status of line inversion display tone. LREV command : line inversion display ON/OFF setting. LREV=”0”: normal display LREV=”1”: line inversion display ON. The area specified by line inversion start/stop address is blinked. The blink type display is controlled by BT command. When line inversion display is ON(LREV=”1”), line inversion start address(LSi) and line inversion stop address(LEi) should be set as following condition. LSi ≤ LEi - (1) And following condition is forbidden. LEi < LSi - (2) |
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