HM17CM256 datasheet(34/111 Pages) HYNIX

34 / 111 page

HM17CM256

- 34 -

(14)

DISPLAY TIMMING GENERATOR

The display-timing generator makes a timing clock and timing pulses (CL, FLM, FR and CLK) for

internal operation by inputting the original oscillating clock CK or by the oscillating circuit.

By setting up Master / Slave mode (M/S), the state of timing pulse pins and the timing generator

changes.

Display timing pulse pins and generator status

M/S port

mode

CL port

FR port

FLM port CLK port

Timing generator status

Slave

Input

CL, FLM, FR signal generator stop

Master

Output

Operating status

(15)

SIGNAL GENERATION OF DISPLAY LINE COUNTER, DISPLAY DATA LATCH CIRCUIT.

The latch signal from line counter clock to display data latch circuit is generated from display clock

(CL).

Synchronized with the display clock, the line addresses of Display RAM are generated and

384-bit display data are latched to display-data latching circuit and then output to the LCD drive

circuit (SEG output port).

Read-out of the display data to the LCD drive circuit is completely independent of MPU side and so

MPU can access it with no relationship with the read-out operation of the display data.

(16)

GENERATION OF THE ALTERNATED SIGNAL(FR), SYNCHRONOUS SIGNAL(FLM).

The alternated signal (FR) and synchronous signal (FLM) are generated from the display clock

(CL).

The FLM generates alternated drive waveform to the LCD drive circuit per frame at normal

state ( inverse FR signal level per 1 frame ).

But by setting up data (n-1) on n-line inversion

When this HM17CM256 is used in multi-chip application, the signals of CL, FLM, FR and CLK

must be sent from master side to slave side.

(17)

DISPLAY DATA LATCH CIRCUIT

This circuit latches the display data from display RAM to LCD driver circuit temporarily per every

common period.

Normal / reverse display, display ON/OFF, and display all on command are done

by controlling data in this latch.

And no data within display RAM changes.

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