HM17CM256 datasheet(19/111 Pages) HYNIX

19 / 111 page

HM17CM256

- 19 -

(6) DDRAM addressing

This IC includes display memory

Bit mapped that is composed of 1024 bit of X direction

(8bit

×128) and 82bit of Y direction.

In gray mode, neighboring 3-bit data or 2-bit data are displayed by segment driver with 8 grays or

4 grays, respectively.

3 outputs of segment driver compose 1 pixel of RGB and 128

×82 pixels are displayed with 256

color (8gray

×8gray×4gray).

Address area of X direction is varied according to accessed data length.

The area of X direction

is 0H~7FH at 8bit access mode and 0H~3FH at 16bit access mode.

•

8BIT access

X-address

7EH

7FH

0 H

8bit

Y-address

51H

8bit

•

16 BIT access

X-address

3FH

0 H

16bit

Y-address

51H

16bit

In the Black & white mode, the MSBs of 3 bit and 2 bit corresponding with RGB are used to

display data. And so, 128x82 dot gray display or 384 x 82 B/W mode display is possible.

Display RAM is accessed with X address and Y address from CPU by 8 bit or 16 bit unit.

X address and Y address can be increased automatically by setting status of control register.

The address is increased per every read and write of display RAM by CPU. ( Please see detail

description at command function.)

X direction is selected by X address and Y direction is selected by Y address. Please do not set

the address on non-effective area and it is forbidden to set address on outside area in each case.

384bit display data of Y direction are read out to display latch at rising edge of CL signal per 1 line

cycle and this data comes out from display latch at falling edge of CL signal.

Display start line address register is preset to line counter at “H” state of FLM signal which changes

per one frame cycle and the address is counted up with synchronized CL input.

Display line address counter is synchronized by timing signals of LCD driver, and it operates

independently with X, Y address counters.

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