HM17CM256 datasheet(15/111 Pages) HYNIX

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HM17CM256

- 15 -

(1-5)

4 line type serial interface

4 line serial interface by SDA and SCL is possible at chip selection state (CS=”L”)

When chip is not selected, internal shift register and counter are reset to initial value.

Serial input data from SDA are latched at the rising edge of serial clock (SCL) in the sequence

of D7,

, D1, D0 and converted into 8-bit parallel data at the rising edge of 8th serial clock.

Serial data (SDA) are identified to display data or command by RS input.

TABLE

Data contents

command

Display data

Make serial clock (SCL) “L” at the non-access period and after 8bit data transfer.

SDA and SCL signals are sensitive to external noise.

To prevent mal-function, chip selector

state should be released (CS = “H”) after 8bit data transfer as shown in the following figure.

4 line serial interface

(1-6)

3 line type serial interface

3-line serial interface by SDA and SCL is possible at chip selection state (CS=”L”)

When chip is not selected, internal shift register and counter are reset to initial value.

Input data from SDA are latched at the rising edge of serial clock (SCL) in the sequence of RS,

,D1, D0,

and converted to 8bit parallel data and handled at the rising edge of 9th serial

clock.

Serial data (SDA) are identified to display data or command by RS bit data at the rising of first

serial clock (SCL) and state of command data bit polarity shift pin (SPOL).

TABLE

SPOL=L

SPOL=H

Data identify

Display data

command

Display data

VALID

SDA

SCL

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