HM17CM256 datasheet(18/111 Pages) HYNIX

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HM17CM256

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(3) Read out of internal register

Read out is possible not only from DDRAM, but also from the internal register.

Addresses for

read (0~FH) are allocated in each register.

Read out is executed after writing read-out register address to internal register.

Internal register read out sequence

When register is read out, upper 4 bit data are “1111”.

Non-used bits of active registers are “0”.

When non-used registers are read out, upper 4 bits are “1111” and lower 4 bits are “0000”.

(4) 16 bit data access to DDRAM

It is possible to write in DDRAM by 16-bits access with the data of 16 bits data bus D0~D15.

16 bits data access mode is possible by setting the value of WLS register to “1”.

TABEL

WLS

Acess mode

8 bit

16 bit

Each command should be set to 8-bits(D0~D7) as well as to 16-bit access mode.

16-bit access is available at display RAM access.

(5) Display start line register

When displaying the DDRAM data, it is the contents of Y address register that is corresponding to

display start line.

The data of Y address is displayed on the display start line depending on the value of the shift

command register and the display start line register.

The data of this register are preset to the display line counter per FLM signal transition.

Line counter is counted up in synchronization with CL input and generates line address that read

out 384bit data from DDRAM to LCD driver circuit.

D0~D7

Address set

for

Internal

Address set

for

Internal

RE register set:100

Internal register read address set

set RE of register to be read out

Internal register read

HM17CM256 датащи(PDF) 18 Page - Hynix Semiconductor