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HM17CM256 датащи(PDF) 17 Page - Hynix Semiconductor |
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HM17CM256 датащи(HTML) 17 Page - Hynix Semiconductor |
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17 / 111 page ![]() HM17CM256 - 17 - (2) DDRAM and internal register access DDRAM and internal register are accessed by data bus D0~D7(D0~D15), chip select pin (CS), DDRAM / register select pin (RS), read / write control pin (RD) or WR pin. When CS=“H”, it is in non-selective state and DDRAM and internal register access is impossible. During access, Set CS=“L”. Access selection to DDRAM or internal register is controlled by RS input. TABLE RS Data contents L Display RAM data H Internal command register Write process starts after address setting and then the data on the 8bit data bus D0~D7 or 16bit data bus D0~D15 will be written in by CPU. The data is written at the rising edge of WR (80 series) or falling edge of E (68 series). Internally, bus holder data is processed to data bus and data are written to bus holder from CPU until next cycle. After address setting, data of assigned address are read at the 1st and 3rd clock, which means it needs dummy read at the 2nd clock. There are rules at reading data out of display RAM, after address setting, the data of assigned address is shown directly after the end of the read command, so pay attention that assigned data is available at 2nd timing step. In other words, 1 cycle dummy read is needed after address setting and write cycle. DATA WRITE IN OPERATION DATA READ OUT OPERATION caution) When 16 bit mode, do write in and read out by 16 bit not only RAM access but also command setting. n n+2 D0~D15 WR BUS HOLDER WR n n+1 n+2 n+3 n+4 n+1 n+3 n+4 D0~D7(D0~D15) RD n n n+1 n+2 WR address set n dummy read data read n address data read n+1 address data read n+2 address |
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