HM17CM256 datasheet(36/111 Pages) HYNIX

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HM17CM256

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LCD DRIVER CIRCUIT

This drive circuit generates four levels of LCD drive voltage.

The circuit has 384 segment outputs

and 82 common outputs and outputs combined display data and FR signal.

Two of common outputs(COMI0,COMI1) are for pictograph marker display only.

The common

drive circuit that has shift register and outputs common scan signals sequentially.

(20)

DUMMY SEGMENT DRIVER CIRCUIT

Segment driver circuit has 6 dummy output ( SEGSA0 ~ SEGSA3, SEGSB0 ~ SEGSB3, SEGSC0 ~

SEGSC3 ) at each edge side.

Normally, the segment driver output is generated by memorized

RAM data but there are no RAMs but registers for dummy segment driver. There are 8 bit registers

correspond to SEGSA0, SEGSB0, SEGSC0 and drive LCD with same level to Y direction. ( SEGSA1

~ SEGSA3, SEGSB1 ~ SEGSB3, SEGSC1 ~ SEGSC3 are the same function. )

SEGSA0 ~ SEGSA3 port is used same gradation palette with SEGA0 ~ SEGA127, SEGSB0 ~

SEGSB3 with SEGB0 ~ SEGB127 , and SEGSC0 ~ SEGSC3 with SEGC0 ~ SEGC127

This circuit is effective at display of boundary or background display.

The dummy segment

drivers do not depend on LREV polarity but ALLON and REV command for display

There are 4-byte registers for dummy segment driver, SEGSA0 ~ SEGSA3, SEGSB0 ~ SEGSB3,

SEGSC0 ~ SEGSC3, If you want to access this register, please use DMY =”1” command.

68 series

80 series

DMY

R/W

Function

Read out display data

Write in display data

Read out dummy segment register

Write in dummy segment register

There are the same rules at read out of dummy segment register as display RAM data read out

sequence.

After address setting, the data of assigned address is shown directly after the end of

the read command, so pay attention that assigned data is available at 2nd timing step.

In other

words, there needs 1 cycle dummy read after address set and write cycle.

1 cycle dummy read is necessary for after address setting and write cycle.

When access with DMY=”1”, X address is an effective value at address setting.

There are 4-byte

and so 00H, 01H, 02H, 03H are effective at 8-bit mode and 00H, 01H are effective at 16-bit mode.

The access bears no relation to Y address setting.

When access with DMY=”1”, it is possible that the data is written into register by increment

operation.

notice) more detail information at

DUMMY SEGMENT REGISTER ADDRESS AND BITMAP

(10) Relation

between Display RAM and address

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