HM17CM256 datasheet(16/111 Pages) HYNIX

16 / 111 page

HM17CM256

- 16 -

Serial clock (SCL) should go to “L” at the non-access period and after 9bit data transfer.

SDA and SCL signals are sensitive to external noise.

To prevent miss operation chip

selector state should be released (CS = “H”) after 9bit data transfer as shown in the following

figure.

3line serial interface

(1-7)

One systematization of CS when serial interface is selected

In the multi-chip operation (master/slave) mode with serial I/F connection, one CS signal

controls two chips to reduce control signal.

Connect extended chip selection port (EXCS) of master chip to EXCS port ( input at slave

device and output at master device mode ) of slave chip.

When EXCS is “L”, master chip cannot accept

command except for EXCS control; at this

point, only slave chip can be controlled.

Slave device control is possible when CS = “L” period within EXCS = “L” state.

SDA

SCL

SDA

SCL

M/S

P/S

SMODE

SPOL

EXCS

(MASTER)

SDA

SCL

M/S

P/S

SMODE

SPOL

EXCS

(SLAVE)

SDA

SCL

EXCS: expand CS signal ( input port )

Master device : output port

Slave device : input port

(input port)

P/S=0: serial I/F

P/S=1: parallel I/F

P/S: parallel . serial selection port

(input port)

M/S=0: slave operation

M/S=1: master operation

M/S: master . slave selection port

(input port)

SMODE=0: 4 line serial I/F

SMODE=1: 3 line serial I/F

SMODE: serial I/Fmode selection port

(input port)

Access display RAM at SPOL=0:RS=0

Access display RAM at SPOL=1:RS=1

SPOL:command data bit polarity selection port

At 3 line serial I/F mode

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