AS3543-ECTP datasheet(24/92 Pages) AMSCO

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AS3543 3v2

Data Sheet - D e t a i l e d D e s c r i p t i o n - A u d i o F u n c t i o n s

8.4.9

8.5

DAC, ADC and I2S Digital Audio Interface

8.5.1

Input

The AFE receives serialized audio data for the DAC via pin SDI. The output of the DAC is fed through a volume control

to the mixer stage and to the multiplexers of line output and headphone amplifiers or direct to these output stages.

This serialized audio data is a digital audio data stream with the left and the right audio channels multiplexed into one

bit-stream. Via pin LRCK the alignment clock is input to the DAC digital filters. LRCK (Left Right Clock) indicates

whether the serial bit-stream received via pin SDI, represents right channel or left channel audio data. Via pin SCLK

the bit clock for the serial bit-stream is signalled. SDI and LRCK are synchronous with SCLK. SDI, LRCK and SCLK

are inputs; SDO is not used.

The volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain

can be set from –40.5dB to +6dB. The stage is set to mute by default. If the DAC input is not enabled, the volume set-

tings are set to their default values. Changing the volume and mute control can only be done after enabling the input.

8.5.2

Output

This block consists of an audio multiplexer where the signal, which should be recorded, can be selected. The output is

then fed through a volume control to the audio ADC. The digital output is done via an I2S interface.

The AFE sends serialized audio data from the ADC via pin SDO. This serialized audio data is a digital audio data

stream with the left and the right audio channels multiplexed into one bit-stream. Via pin LRCK the alignment clock is

signalled to the connected devices (e.g. CPU). LRCLK (Left Right Clock) indicates whether the serial bit-stream sent

via pin SDI, presents right channel or left channel audio data. Via pin SCLK the bit clock for the serial bit-stream is sig-

nalled. SDO and LRCK are synchronous with SCLK. SDO is an output; LRCK and SCK are inputs; SDI is not used.

The volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain

can be set from –34.5dB to +12dB. The stage is set to mute by default. If the ADC output is not enabled, the volume

settings are set to their default values. Changing the volume and mute control can only be done after enabling the

input.

The I2S output uses the same clocks as the I2S input. The sampling rate therefore depends also on the input sampling

rate. The exact ratio can be set in register 11h.

The SDO output can be configured to operate in push/pull (3 different driver strengths) or to be tri-state. For a more

detailed description of the GPIO functionality of this pin please refer to chapter GPIO Pins on page 50.

Over current limit

HPR/HPL pins

HPCM pin, @1.8V

70mA

110mA

Over current limit

HPR/HPL pins

HPCM pin, @2.7V

140mA

220mA

PSRRHP

Power Supply Rejection

Ratio

200Hz-20kHz, 720mVpp, RL=16

AHPMUTE

Mute Attenuation

100

Table 14. Headphone Related Register

Name

Base

Offset

Description

OUT_R

2-wire serial

02h

Right HP Output volume and over-current settings

OUT_L

2-wire serial

03h

Left HP Output volume settings, enable and detection control

AudioSet2

2-wire serial

15h

Auto fading timing settings

AudioSet3

2-wire serial

16h

Power options, common mode buffer enable

IRQENRD_3

2-wire serial

26h

Interrupt settings for over current and HP detection

Table 13. Headphone Output Parameter (Continued)

Symbol

Parameter

Condition

Min

Typ

Max

Unit

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