AS3543-ECTP datasheet(78/92 Pages) AMSCO

78 / 92 page

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Revision 1.11

77 - 91

AS3543 3v2

Data Sheet - R e g i s t e r D e f i n i t i o n

Table 79. SYSTEM Register

Name

Base

Default

SYSTEM

2-wire serial

41h

Offset: 20h

SYSTEM Register

This register is reset at a AVDD27-POR.

Bit

Bit Name

Default

Access

Bit Description

7:4

Design_Version<3:0>

0100

AFE number to identify the design version

0100: for chip version 3v0

HB_WD_ON

R/W

Heartbeat (HBT) Watchdog

The watchdog counter will be reset by a rising edge at the

HBT input pin which has to occur at least every 500ms. If the

watchdog counter is not reset, the AFE will be powered down.

0: HBT watchdog is disabled

1: HBT watchdog is enabled

JTEMP_OFF

R/W

Junction temperature supervision (level can be set in register

21h)

0: temperature supervision enabled

1: temperature supervision disabled

I2C_WD_ON

R/W

2-wire serial interface watchdog

To reset the watchdog counter a 2-wire serial read operation

has to be performed at least every 500ms. If the watchdog

counter is not reset, the AFE will be powered down.

0: watchdog is disabled

1: watchdog is enabled

PWR_HOLD

R/W

0: power up hold is cleared and AFE will power down

1: is automatically set to on after power on

Table 80. SUPERVISOR Register

Name

Base

Default

SUPERVISOR

2-wire serial

00h

Offset: 21h

SUPERVISOR Register

This register is reset at a AVDD27-POR.

Bit

Bit Name

Default

Access

Bit Description

SD_TIME

0100

R/W

Sets the emergency shut-down time invoked by PWRUP.

0: 5.4sec

1: 10.9sec

BVDDlow_SD_OFF

R/W

0: BVDDlow shut down enalbed

1: BVDDlow shut down disabled

n/a

4:0

JTEMP_SUP<4:0>

R/W

Sets the threshold for junction temperature emergency

shutdown and junction temperature interrupt

Invoke shutdown at: JTemp_SD=140-JTEMP_Sup*5

°C

Invoke interrupt at: JTemp_IRQ=120-JTEMP_Sup*5

°C

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