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AS3543-ECTP датащи(PDF) 68 Page - ams AG

номер детали AS3543-ECTP
подробное описание детали  High End Stereo Audio Codec wi th System PMU
PDF  92 Pages
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производитель  AMSCO [ams AG]
домашняя страница  http://www.ams.com
Logo AMSCO - ams AG

AS3543-ECTP датащи(HTML) 68 Page - ams AG

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Revision 1.11
67 - 91
AS3543 3v2
Data Sheet - R e g i s t e r D e f i n i t i o n
3:2
DVM_CVDD2<1:0>
00
R/W
Configures the dynamic voltage management (output voltage
slope) for CVDD2
00: immediate change of the output voltage
01: 42us/step
02:166us/step
03: 666us/step
1:0
DVM_CVDD1<1:0>
00
R/W
Configures the dynamic voltage management (output voltage
slope) for CVDD1
00: immediate change of the output voltage
01: 42us/step
02:166us/step
03: 666us/step
Table 62. PVDD1 Register
Name
Base
Default
PVDD1
2-wire serial
00h
Offset: 18h-1
PVDD1 Control Register
This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first.
This register is reset at a AVDD27-POR.
Bit
Bit Name
Default
Access
Bit Description
7
PVDD1_OFF
0
R/W
Switches off PVDD1 regulator
0: normal mode
1: PVDD1 switched off
6
ILIM_H_PVDD1
0
R/W
Selects the higher current limit for PVDD1
0: default mode, 100mA
1: 200mA mode
5
PRG_PVDD1
0
R/W
Selects the output voltage control mode for PVDD1
0: PVDD1 is in default mode controlled by pin VPRG2
1: PVDD1 is register controlled (Reg. 18-1h)
4:0
VSEL_PVDD1<4:0>
00000
R/W
Sets the LDO output voltage in register control mode (default
voltage of the regulator is selcted by pin VPROG2)
0x00-0x0F: 1.2V+VSEL*50mV ->(1.2V - 1.95V)
0x10-0x1F: 2.0V + (VSEL-0x10)*100mV -> (2.0V-3.5V)
Table 61. DCDC_Cntr Register
Name
Base
Default
DCDC_Cntr
2-wire serial
00h
Offset: 17h-7
DC/DC Step Down Control Register
This is an extended register and needs to be enabled by writing 111b to Reg. 1Ch first.
This register is reset at a AVDD27-POR.
Bit
Bit Name
Default
Access
Bit Description



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