AS3543-ECTP datasheet(83/92 Pages) AMSCO

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Revision 1.11

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AS3543 3v2

Data Sheet - R e g i s t e r D e f i n i t i o n

RTC_WD

(level)

Real time clock watchdog interrupt setting

0: disable

1: enable

Real time clock watchdog interrupt reading

0: RTC o.k.

1: RTC oszillator was stopped, RTC not longer valid

The interrupt gets set in hibernation or during power-up even if

the interrupt is not enabled thus allowing to recognise a

change of the battery connected to BVDDR during hibernation

or shutdown. For a valid reading, the interrupt has to be

enabled first.

BVDD_LOW

(level)

BVDD under-voltage supervisor interrupt setting

0: disable

1: enable

BVDD supervisor interrupt reading

0: BVDD is above brown out level

1: BVDD has reached brown out level

The threshold can be set in the SUPERVISOR register (21h)

Table 85. Fourth Interrupt Register

Name

Base

Default

IRQENRD_3

2-wire serial

00h

Offset: 26h

Fourth Interrupt Register

Please be aware that writing to this register will enable/disable the

corresponding interrupts, while reading gets the actual interrupt status and

will clear the register at the same time. It is not possible to read back the

interrupt enable/disable settings. This register is reset at a AVDD27-POR.

Bit

Bit Name

Default

Access

Bit Description

JTEMP_HIGH

(level)

Supervisor junction over-temperature interrupt setting

0: disable

1: enable

Supervisor junction over-temperature interrupt reading

0: chip temperature below threshold

1: chip temperature has reached the threshold

The threshold can be set in the SUPERVISOR register (21h)

n/a

Table 84. Thrid Interrupt Register

Name

Base

Default

IRQENRD_2

2-wire serial

00h

Offset: 25h

Third Interrupt Register

Please be aware that writing to this register will enable/disable the

corresponding interrupts, while reading gets the actual interrupt status and

will clear the register at the same time. It is not possible to read back the

interrupt enable/disable settings. This register is reset at a AVDD27-POR.

Bit

Bit Name

Default

Access

Bit Description

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