AS3543-ECTP datasheet(64/92 Pages) AMSCO

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Revision 1.11

63 - 91

AS3543 3v2

Data Sheet - R e g i s t e r D e f i n i t i o n

Table 54. DAC_IF Register

Name

Base

Default

DAC_IF

2-wire serial

00h

Offset: 12h

DAC Interface Register

Configures the DAC interface and digital gain on the I2S input stream.

This register is reset at a AVDD27-POR.

Bit

Bit Name

Default

Access

Bit Description

I2S_DIRECT

R/W

0: I2S master clock is generated by the internal PLL

1: signal on MCLK is used as I2S master clock

I2S_LOOP

R/W

0: normal operation

1: ADC output is connected to DAC input

I2S_ATTEN

R/W

0: normal operation

1: digital attenuation on I2S input data (SDI) enabled

4:0

SDI_ATTEN<4:0>

00000

R/W

digital volume settings I2S input data (SDI), adjustable in 32

steps @ 1.5dB; gain from SDI pin to DAC input

11111: -1.5 dB gain

11110: -3 dB gain

00001: -46.5 dB gain

00000: -48.0 dB gain

Table 55. AudioSet1 Register

Name

Base

Default

AudioSet1

2-wire serial

00h

Offset: 14h

First Audio Set Register

Powers the various audio inputs and outputs UP or DOWN.

Caution:

This control register resets and holds LineIn, DAC, and ADC related regis-

ters in reset. After activation the required register settings need to be re-

programmed.

This register is reset at a AVDD27-POR.

Bit

Bit Name

Default

Access

Bit Description

ADC_ON

R/W

0: ADC powered down

1: ADC enabled for recording

DAC_ON

R/W

0: DAC powered down

1: DAC enabled for playback

DAC_GST_ON

R/W

0: DAC gainstage powered down

1: DAC gainstage enabled (needed for playback via mixer)

4:3

n/a

LIN_ON

R/W

0: Line Input powered down

1: Line Input enabled

n/a

MIC_ON

R/W

0: Microphone Input powered down

1: Microphone Input enabled

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