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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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A3P030 датащи(PDF) 115 Page - Microsemi Corporation |
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A3P030 датащи(HTML) 115 Page - Microsemi Corporation |
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115 / 220 page  ProASIC3 Flash Family FPGAs Revision 13 2-101 Timing Characteristics Table 2-118 • FIFO (for all dies except A3P250) Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –2 –1 Std. Units tENS REN, WEN Setup Time 1.34 1.52 1.79 ns tENH REN, WEN Hold Time 0.00 0.00 0.00 ns tBKS BLK Setup Time 0.19 0.22 0.26 ns tBKH BLK Hold Time 0.00 0.00 0.00 ns tDS Input Data (WD) Setup Time 0.18 0.21 0.25 ns tDH Input Data (WD) Hold Time 0.00 0.00 0.00 ns tCKQ1 Clock High to New Data Valid on RD (flow-through) 2.17 2.47 2.90 ns tCKQ2 Clock High to New Data Valid on RD (pipelined) 0.94 1.07 1.26 ns tRCKEF RCLK High to Empty Flag Valid 1.72 1.96 2.30 ns tWCKFF WCLK High to Full Flag Valid 1.63 1.86 2.18 ns tCKAF Clock High to Almost Empty/Full Flag Valid 6.19 7.05 8.29 ns tRSTFG RESET Low to Empty/Full Flag Valid 1.69 1.93 2.27 ns tRSTAF RESET Low to Almost Empty/Full Flag Valid 6.13 6.98 8.20 ns tRSTBQ RESET Low to Data Out Low on RD (flow-through) 0.92 1.05 1.23 ns RESET Low to Data Out Low on RD (pipelined) 0.92 1.05 1.23 ns tREMRSTB RESET Removal 0.29 0.33 0.38 ns tRECRSTB RESET Recovery 1.50 1.71 2.01 ns tMPWRSTB RESET Minimum Pulse Width 0.21 0.24 0.29 ns tCYC Clock Cycle Time 3.23 3.68 4.32 ns FMAX Maximum Frequency for FIFO 310 272 231 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. |
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