AGLP030 datasheet(12/134 Pages) MICROSEMI

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IGLOO PLUS Device Family Overview

1-6

Revision 16

SRAM and FIFO

IGLOO PLUS devices (except AGLP030 devices) have embedded SRAM blocks along their north side.

Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are

256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports

that can be configured with different bit widths on each port. For example, data can be sent through a

4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device

JTAG port (ROM emulation mode) using the UJTAG macro (except in AGLP030 devices).

In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM

block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width

and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and

Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control

unit contains the counters necessary for generation of the read and write address pointers. The

embedded SRAM/FIFO blocks can be cascaded to create larger configurations.

PLL and CCC

IGLOO PLUS devices provide designers with very flexible clock conditioning circuit (CCC) capabilities.

Each member of the IGLOO PLUS family contains six CCCs. One CCC (center west side) has a PLL.

The AGLP030 device does not have a PLL or CCCs; it contains only inputs to six globals.

The six CCC blocks are located at the four corners and the centers of the east and west sides. One CCC

(center west side) has a PLL.

The four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine

access.

The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs

located near the CCC that have dedicated connections to the CCC block.

The CCC block has these key features:

•

Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz

•

Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz

•

2 programmable delay types for clock skew minimization

•

Clock frequency synthesis (for PLL only)

Additional CCC specifications:

•

Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider

configuration (for PLL only).

•

Output duty cycle = 50% ± 1.5% or better (for PLL only)

•

Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global

network used (for PLL only)

•

Maximum acquisition time is 300 µs (for PLL only)

•

Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL only)

•

Four precise phases; maximum misalignment between adjacent phases (for PLL only) is 40 ps ×

250 MHz / fOUT_CCC

Global Clocking

IGLOO PLUS devices have extensive support for multiple clocking domains. In addition to the CCC and

PLL support described above, there is a comprehensive global clock distribution network.

Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant

global networks. The VersaNets can be driven by the CCC or directly accessed from the core via

multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid

distribution of high-fanout nets.

I/Os with Advanced I/O Standards

The IGLOO PLUS family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.2

V, 1.5 V, 1.8 V, 2.5 V, 3.0 V wide range, and 3.3 V). IGLOO PLUS FPGAs support many different I/O

standards.

The I/Os are organized into four banks. All devices in IGLOO PLUS have four banks. The configuration

of these banks determines the I/O standards supported.

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