AGLP030 datasheet(73/134 Pages) MICROSEMI

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IGLOO PLUS Low Power Flash FPGAs

Revision 16

2-59

1.2 V DC Core Voltage

Table 2-86 • AGLP125 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter

Description

Std.

Units

Min.1

Max.2

tRCKL

Input Low Delay for Global Clock

1.36

1.71

tRCKH

Input High Delay for Global Clock

1.39

1.82

tRCKMPWH

Minimum Pulse Width High for Global Clock

1.18

tRCKMPWL

Minimum Pulse Width Low for Global Clock

1.15

tRCKSW

Maximum Skew for Global Clock

0.43

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,

located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully

loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Table 2-87 • AGLP030 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V

Parameter

Description

Std.

Units

Min.1

Max.2

tRCKL

Input Low Delay for Global Clock

1.80

2.09

tRCKH

Input High Delay for Global Clock

1.88

2.27

tRCKMPWH

Minimum Pulse Width High for Global Clock

1.40

tRCKMPWL

Minimum Pulse Width Low for Global Clock

1.65

tRCKSW

Maximum Skew for Global Clock

0.39

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,

located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully

loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

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