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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AGLP030 датащи(PDF) 91 Page - Microsemi Corporation |
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AGLP030 датащи(HTML) 91 Page - Microsemi Corporation |
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91 / 134 page  IGLOO PLUS Low Power Flash FPGAs Revision 16 2-77 1.2 V DC Core Voltage Table 2-97 • FIFO Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Parameter Description Std. Units tENS REN, WEN Setup Time 3.44 ns tENH REN, WEN Hold Time 0.26 ns tBKS BLK Setup Time 0.30 ns tBKH BLK Hold Time 0.00 ns tDS Input Data (WD) Setup Time 1.30 ns tDH Input Data (WD) Hold Time 0.41 ns tCKQ1 Clock High to New Data Valid on RD (flow-through) 5.67 ns tCKQ2 Clock High to New Data Valid on RD (pipelined) 3.02 ns tRCKEF RCLK High to Empty Flag Valid 6.02 ns tWCKFF WCLK High to Full Flag Valid 5.71 ns tCKAF Clock High to Almost Empty/Full Flag Valid 22.17 ns tRSTFG RESET Low to Empty/Full Flag Valid 5.93 ns tRSTAF RESET Low to Almost Empty/Full Flag Valid 21.94 ns tRSTBQ RESET Low to Data Out Low on RD (flow-through) 3.41 ns RESET Low to Data Out Low on RD (pipelined) 3.41 ns tREMRSTB RESET Removal 1.02 ns tRECRSTB RESET Recovery 5.48 ns tMPWRSTB RESET Minimum Pulse Width 1.18 ns tCYC Clock Cycle Time 10.90 ns FMAX Maximum Frequency for FIFO 92 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. |
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