AGLP030 datasheet(26/134 Pages) MICROSEMI

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IGLOO PLUS DC and Switching Characteristics

2-12

Revision 16

Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For more

accurate and detailed power estimations, use the SmartPower tool in Libero SoC software.

The power calculation methodology described below uses the following variables:

•

The number of PLLs as well as the number and the frequency of each output clock generated

•

The number of combinatorial and sequential cells used in the design

•

The internal clock frequencies

•

The number and the standard of I/O pins used in the design

•

The number of RAM blocks used in the design

•

Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-19 on

page 2-14.

•

Enable rates of output buffers—guidelines are provided for typical applications in Table 2-20 on

page 2-14.

•

Read rate and write rate to the memory—guidelines are provided for typical applications in

Table 2-20 on page 2-14. The calculation should be repeated for each clock domain defined in the

design.

Methodology

Total Power Consumption—PTOTAL

PTOTAL = PSTAT + PDYN

PSTAT is the total static power consumption.

PDYN is the total dynamic power consumption.

Total Static Power Consumption—PSTAT

PSTAT = (PDC1 or PDC2 or PDC3) + NBANKS * PDC5

NBANKS is the number of I/O banks powered in the design.

Total Dynamic Power Consumption—PDYN

PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL

Global Clock Contribution—PCLOCK

PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK

NSPINE is the number of global spines used in the user design—guidelines are provided in

the "Spine Architecture" section of the Global Resources chapter in the IGLOO PLUS FPGA

Fabric User's Guide

Table 2-18 • Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices

For IGLOO PLUS V2 Devices, 1.2 V Core Supply Voltage

Parameter

Definition

Device-Specific Static Power (mW)

AGLP125

AGLP060

AGLP030

PDC1

Array static power in Active mode

See Table 2-12 on page 2-8

PDC2

Array static power in Static (Idle) mode

See Table 2-11 on page 2-8

PDC3

Array static power in Flash*Freeze mode

See Table 2-9 on page 2-7

PDC4

Static PLL contribution

0.901

PDC5

Bank quiescent power (VCCI-dependent)

See Table 2-12 on page 2-8

Notes:

1. This is the minimum contribution of the PLL when operating at lowest frequency.

2. For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet

calculator or the SmartPower tool in Libero SoC software.

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