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18F8680 датащи(PDF) 71 Page - Microchip Technology

номер детали 18F8680
подробное описание детали  64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module
PDF  496 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

18F8680 датащи(HTML) 71 Page - Microchip Technology

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 2004 Microchip Technology Inc.
DS30491C-page 69
PIC18F6585/8585/6680/8680
SPBRG
USART Baud Rate Generator
0000 0000
38, 239
RCREG
USART Receive Register
0000 0000
38, 241
TXREG
USART Transmit Register
0000 0000
38, 239
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
0000 0010
38, 230
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
38, 231
EEADRH
EE Adr Register High
---- --00
38, 105
EEADR
Data EEPROM Address Register
0000 0000
38, 105
EEDATA
Data EEPROM Data Register
0000 0000
38, 105
EECON2
Data EEPROM Control Register 2 (not a physical register)
---- ----
38, 105
EECON1
EEPGD
CFGS
FREE
WRERR
WREN
WR
RD
00-0 x000
38, 102
IPR3
IRXIP
WAKIP
ERRIP
TXB2IP/
TXBnIP
TXB1IP
TXB0IP
RXB1IP/
RXBnIP
RXB0IP/
FIFOWMIP
1111 1111
39, 122
PIR3
IRXIF
WAKIF
ERRIF
TXB2IF/
TXBnIF
TXB1IF
TXB0IF
RXB1IF/
RXBnIF
RXB0IF/
FIFOWMIF
0000 0000
39, 116
PIE3
IRXIE
WAKIE
ERRIE
TXB2IE/
TXBnIE
TXB1IE
TXB0IE
RXB1IE/
RXBnIE
RXB0IE/
FIFOWMIE
0000 0000
39, 119
IPR2
—CMIP
EEIP
BCLIP
LVDIP
TMR3IP
CCP2IP
-1-1 1111
39, 121
PIR2
—CMIF
EEIF
BCLIF
LVDIF
TMR3IF
CCP2IF
-0-0 0000
39, 115
PIE2
—CMIE
EEIE
BCLIE
LVDIE
TMR3IE
CCP2IE
-0-0 0000
39, 118
IPR1
PSPIP
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
0111 1111
39, 120
PIR1
PSPIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
39, 114
PIE1
PSPIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
39, 117
MEMCON(3)
EBDIS
—WAIT1
WAIT0
—WM1
WM0
0-00 --00
39, 94
TRISJ(3)
Data Direction Control Register for PORTJ
1111 1111
39, 151
TRISH(3)
Data Direction Control Register for PORTH
1111 1111
39, 148
TRISG
Data Direction Control Register for PORTG
---1 1111
39, 145
TRISF
Data Direction Control Register for PORTF
1111 1111
39, 141
TRISE
Data Direction Control Register for PORTE
1111 1111
39, 138
TRISD
Data Direction Control Register for PORTD
1111 1111
39, 135
TRISC
Data Direction Control Register for PORTC
1111 1111
39, 131
TRISB
Data Direction Control Register for PORTB
1111 1111
39, 128
TRISA
—TRISA6(1)
Data Direction Control Register for PORTA
-111 1111
39, 125
LATJ(3)
Read PORTJ Data Latch, Write PORTJ Data Latch
xxxx xxxx
39, 151
LATH(3)
Read PORTH Data Latch, Write PORTH Data Latch
xxxx xxxx
39, 148
LATG
Read PORTG Data Latch, Write PORTG Data Latch
---x xxxx
39, 145
LATF
Read PORTF Data Latch, Write PORTF Data Latch
xxxx xxxx
39, 141
LATE
Read PORTE Data Latch, Write PORTE Data Latch
xxxx xxxx
39, 138
LATD
Read PORTD Data Latch, Write PORTD Data Latch
xxxx xxxx
39, 133
LATC
Read PORTC Data Latch, Write PORTC Data Latch
xxxx xxxx
39, 131
LATB
Read PORTB Data Latch, Write PORTB Data Latch
xxxx xxxx
39, 128
LATA
—LATA6(1)
Read PORTA Data Latch, Write PORTA Data Latch(1)
-xxx xxxx
39, 125
TABLE 4-3:
REGISTER FILE SUMMARY (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on page:
Legend:
x
= unknown, u = unchanged, – = unimplemented, q = value depends on condition
Note
1:
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator
modes.
2:
Bit 21 of the TBLPTRU allows access to the device configuration bits.
3:
These registers are unused on PIC18F6X80 devices; always maintain these clear.
4:
These bits have multiple functions depending on the CAN module mode selection.
5:
Meaning of this register depends on whether this buffer is configured as transmit or receive.
6:
RG5 is available as an input when MCLR is disabled.
7:
This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2.



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