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18F8680 датащи(PDF) 47 Page - Microchip Technology |
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18F8680 датащи(HTML) 47 Page - Microchip Technology |
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47 / 496 page ![]() 2004 Microchip Technology Inc. DS30491C-page 45 PIC18F6585/8585/6680/8680 B3D4(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B3D3(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B3D2(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B3D1(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B3D0(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B3DLC(7) PIC18F6X8X PIC18F8X8X -xxx xxxx -uuu uuuu -uuu uuuu B3EIDL(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B3EIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B3SIDL(7) PIC18F6X8X PIC18F8X8X xxxx x-xx uuuu u-uu uuuu u-uu B3SIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B3CON(7) PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu B2D7(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B2D6(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B2D5(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B2D4(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B2D3(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B2D2(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B2D1(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B2D0(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B2DLC(7) PIC18F6X8X PIC18F8X8X -xxx xxxx -uuu uuuu -uuu uuuu B2EIDL(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B2EIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B2SIDL(7) PIC18F6X8X PIC18F8X8X xxxx x-xx uuuu u-uu uuuu u-uu B2SIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B2CON(7) PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu B1D7(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B1D6(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B1D5(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B1D4(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B1D3(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B1D2(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’. 7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2. |
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