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18F8680 датащи(PDF) 44 Page - Microchip Technology |
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18F8680 датащи(HTML) 44 Page - Microchip Technology |
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44 / 496 page ![]() PIC18F6585/8585/6680/8680 DS30491C-page 42 2004 Microchip Technology Inc. TXB0SIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB0CON PIC18F6X8X PIC18F8X8X 0000 0-00 0000 0-00 uuuu u-uu TXB1D7 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB1D6 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB1D5 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB1D4 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB1D3 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB1D2 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB1D1 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB1D0 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB1DLC PIC18F6X8X PIC18F8X8X -x-- xxxx -u-- uuuu -u-- uuuu TXB1EIDL PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB1EIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB1SIDL PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu uuu- uu-u TXB1SIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu -uuu uuuu TXB1CON PIC18F6X8X PIC18F8X8X 0000 0-00 0000 0-00 uuuu u-uu TXB2D7 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D6 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D5 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D4 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D3 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D2 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D1 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D0 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu 0uuu uuuu TXB2DLC PIC18F6X8X PIC18F8X8X -x-- xxxx -u-- uuuu -u-- uuuu TXB2EIDL PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB2EIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB2SIDL PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu uuu- u-uu TXB2SIDH PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu uuu- u-uu TXB2CON PIC18F6X8X PIC18F8X8X 0000 0-00 0000 0-00 uuuu u-uu RXM1EIDL PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’. 7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2. |
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