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18F8680 датащи(PDF) 40 Page - Microchip Technology |
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18F8680 датащи(HTML) 40 Page - Microchip Technology |
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40 / 496 page ![]() PIC18F6585/8585/6680/8680 DS30491C-page 38 2004 Microchip Technology Inc. ADRESH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu ADRESL PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 PIC18F6X8X PIC18F8X8X --00 0000 --00 0000 --uu uuuu ADCON1 PIC18F6X8X PIC18F8X8X --00 0000 --00 0000 --uu uuuu ADCON2 PIC18F6X8X PIC18F8X8X 0-00 0000 0-00 0000 u-uu uuuu CCPR1H PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu CCPR2H PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu CCPR2L PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON PIC18F6X8X PIC18F8X8X --00 0000 --00 0000 --uu uuuu CCPAS1 PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu CVRCON PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu CMCON PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu TMR3H PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TMR3L PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu T3CON PIC18F6X8X PIC18F8X8X 0000 0000 uuuu uuuu uuuu uuuu PSPCON PIC18F6X8X PIC18F8X8X 0000 ---- 0000 ---- uuuu ---- SPBRG PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu RCREG PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu TXREG PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu TXSTA PIC18F6X8X PIC18F8X8X 0000 0010 0000 0010 uuuu uuuu RCSTA PIC18F6X8X PIC18F8X8X 0000 000x 0000 000x uuuu uuuu EEADRH PIC18F6X8X PIC18F8X8X ---- --00 ---- --00 ---- --uu EEADR PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu EEDATA PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu EECON2 PIC18F6X8X PIC18F8X8X xx-0 x000 uu-0 u000 uu-0 u000 EECON1 PIC18F6X8X PIC18F8X8X 00-0 x000 00-0 u000 uu-u uuuu TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’. 7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2. |
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