18F8680 datasheet(23/496 Pages) MICROCHIP

23 / 496 page

 2004 Microchip Technology Inc.

DS30491C-page 21

PIC18F6585/8585/6680/8680

PORTJ is a bidirectional I/O port(5).

RJ0/ALE

RJ0

ALE

——

I/O

TTL

Digital I/O.

External memory address latch

enable.

RJ1/OE

RJ1

——

I/O

TTL

Digital I/O.

External memory output enable.

RJ2/WRL

RJ2

WRL

——

I/O

TTL

Digital I/O.

External memory write low control.

RJ3/WRH

RJ3

WRH

——

I/O

TTL

Digital I/O.

External memory write high control.

RJ4/BA0

RJ4

BA0

——

I/O

TTL

Digital I/O.

System bus byte address 0 control.

RJ5/CE

—

I/O

TTL

Digital I/O

External memory chip enable.

RJ6/LB

RJ6

——

I/O

TTL

Digital I/O.

External memory low byte select.

RJ7/UB

RJ7

——

I/O

TTL

Digital I/O.

External memory high byte select.

VSS

9, 25,

41, 56

19, 36,

53, 68

11, 31,

51, 70

—

Ground reference for logic and I/O pins.

VDD

10, 26,

38, 57

2, 20,

37, 49

12, 32,

48, 71

—

Positive supply for logic and I/O pins.

AVSS

—

Ground reference for analog modules.

AVDD

—

Positive supply for analog modules.

—

1, 18,

35, 52

—

No connect.

TABLE 1-2:

PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

Type

Buffer

Type

Description

PIC18F6X8X PIC18F8X8X

TQFP PLCC

TQFP

Legend: TTL

= TTL compatible input

CMOS

= CMOS compatible input or output

= Schmitt Trigger input with CMOS levels

Analog = Analog input

= Input

= Output

= Power

= Open-Drain (no P diode to VDD)

Note 1:

Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only.

Default assignment when CCP2MX is set.

External memory interface functions are only available on PIC18F8X8X devices.

CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is

multiplexed with either RB3 or RC1.

PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices.

PSP is available in Microcontroller mode only.

On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX

configuration bit.

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