MPC8548ECPXATHC datasheet(136/151 Pages) FREESCALE

136 / 151 page

MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9

136

Freescale Semiconductor

System Design Information

level must always be equivalent to VDD, and preferably these voltages are derived directly from VDD

through a low frequency filter scheme such as the following.

There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to

provide independent filter circuits per PLL power supply as illustrated in Figure 57, one to each of the

AVDD pins. By providing independent filters to each PLL the opportunity to cause noise injection from

one PLL to the other is reduced.

This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz

range. It must be built with surface mount capacitors with minimum Effective Series Inductance (ESL).

Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook

of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a

single large value capacitor.

Each circuit must be placed as close as possible to the specific AVDD pin being supplied to minimize noise

coupled from nearby circuits. It must be routed directly from the capacitors to the AVDD pin, which is on

the periphery of the footprint, without the inductance of vias.

Figure 57 through Figure 59 shows the PLL power supply filter circuits.

Figure 57. PLL Power Supply Filter Circuit with PLAT Pins

Figure 58. PLL Power Supply Filter Circuit with CORE Pins

Figure 59. PLL Power Supply Filter Circuit with PCI/LBIU Pins

The AVDD_SRDS signal provides power for the analog portions of the SerDes PLL. To ensure stability of

the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in

following figure. For maximum effectiveness, the filter circuit is placed as closely as possible to the

AVDD_SRDS ball to ensure it filters out as much noise as possible. The ground connection must be near

the AVDD_SRDS ball. The 0.003-µF capacitor is closest to the ball, followed by the two 2.2 µF capacitors,

and finally the 1

 resistor to the board supply plane. The capacitors are connected from AV

DD_SRDS to

VDD

AVDD_PLAT

2.2 µF

GND

Low ESL Surface Mount Capacitors

150



VDD

AVDD_CORE

2.2 µF

GND

Low ESL Surface Mount Capacitors

180



VDD

AVDD_PCI/AVDD_LBIU

2.2 µF

GND

Low ESL Surface Mount Capacitors



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