MPC8548ECPXATHC datasheet(66/151 Pages) FREESCALE

66 / 151 page

MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

of a balanced interchange circuit and ground. In this example, for SerDes output, Vcm_out =

VSD_TX + VSD_TX = (A + B)/2, which is the arithmetic mean of the two complimentary output

voltages within a differential pair. In a system, the common mode voltage may often differ from

one component’s output to the other’s input. Sometimes, it may be even different between the

receiver input and driver output circuits within the same component. It is also referred to as the DC

offset.

Figure 38. Differential Voltage Definitions for Transmitter or Receiver

To illustrate these definitions using real values, consider the case of a CML (current mode logic)

transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing

that goes between 2.5 and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD or

TD) is 500 mVp-p, which is referred as the single-ended swing for each signal. In this example, since the

differential signaling environment is fully symmetrical, the transmitter output’s differential swing (VOD)

has the same amplitude as each signal’s single-ended swing. The differential output signal ranges between

500 and –500 mV, in other words, VOD is 500 mV in one phase and –500 mV in the other phase. The peak

differential voltage (VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p) is 1000 mVp-p.

16.2

SerDes Reference Clocks

The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by

the corresponding SerDes lanes. The SerDes reference clocks inputs are SD_REF_CLK and

SD_REF_CLK for PCI Express and serial RapidIO.

The following sections describe the SerDes reference clock requirements and some application

information.

16.2.1

SerDes Reference Clock Receiver Characteristics

Figure 39 shows a receiver reference diagram of the SerDes reference clocks.

•

The supply voltage requirements for XVDD_SRDS2 are specified in Table 1 and Table 2.

•

SerDes Reference clock receiver reference circuit structure:

Differential Swing, VID or VOD = A – B

A Volts

B Volts

SD_TX or

SD_RX

SD_TX or

SD_RX

Differential Peak Voltage, VDIFFp = |A – B|

Differential Peak-Peak Voltage, VDIFFpp = 2*VDIFFp (not shown)

Vcm = (A + B)/2

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