MPC8548ECPXATHC datasheet(140/151 Pages) FREESCALE

140 / 151 page

MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9

140

Freescale Semiconductor

System Design Information

The platform PLL ratio and e500 PLL ratio configuration pins are not equipped with these default pull-up

devices.

22.9

JTAG Configuration Signals

Correct operation of the JTAG interface requires configuration of a group of system control pins as

demonstrated in Figure 63. Care must be taken to ensure that these pins are maintained at a valid deasserted

state under normal operating conditions as most have asynchronous behavior and spurious assertion gives

unpredictable results.

Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the

IEEE 1149.1 specification, but it is provided on all processors built on Power Architecture technology. The

device requires TRST to be asserted during power-on reset flow to ensure that the JTAG boundary logic

does not interfere with normal chip operation. While the TAP controller can be forced to the reset state

using only the TCK and TMS signals, generally systems assert TRST during the power-on reset flow.

Simply tying TRST to HRESET is not practical because the JTAG interface is also used for accessing the

common on-chip processor (COP), which implements the debug interface to the chip.

The COP function of these processors allow a remote computer system (typically, a PC with dedicated

hardware and debugging software) to access and control the internal operations of the processor. The COP

interface connects primarily through the JTAG port of the processor, with some additional status

monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order

to fully control the processor. If the target system has independent reset sources, such as voltage monitors,

watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be

merged into these signals with logic.

The arrangement shown in Figure 63 allows the COP port to independently assert HRESET or TRST,

while ensuring that the target can drive HRESET as well.

The COP interface has a standard header, shown in Figure 62, for connection to the target system, and is

based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The

connector typically has pin 14 removed as a connector key.

The COP header adds many benefits such as breakpoints, watchpoints, register and memory

examination/modification, and other standard debugger features. An inexpensive option can be to leave

the COP header unpopulated until needed.

There is no standardized way to number the COP header; so emulator vendors have issued many different

pin numbering schemes. Some COP headers are numbered top-to-bottom then left-to-right, while others

use left-to-right then top-to-bottom. Still others number the pins counter-clockwise from pin 1 (as with an

IC). Regardless of the numbering scheme, the signal placement recommended in Figure 62 is common to

all known emulators.

22.9.1

Termination of Unused Signals

Freescale recommends the following connections, when the JTAG interface and COP header are not used:

•TRST must be tied to HRESET through a 0 k

 isolation resistor so that it is asserted when the

system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during

the power-on reset flow. Freescale recommends that the COP header be designed into the system

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