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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8548ECPXATHC датащи(PDF) 29 Page - Freescale Semiconductor, Inc |
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MPC8548ECPXATHC датащи(HTML) 29 Page - Freescale Semiconductor, Inc |
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29 / 151 page  MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor 29 Enhanced Three-Speed Ethernet (eTSEC) A summary of the FIFO AC specifications appears in Table 24 and Table 25. Timing diagrams for FIFO appear in Figure 6 and Figure 7. Figure 6. FIFO Transmit AC Timing Diagram Table 24. FIFO Mode Transmit AC Timing Specification Parameter/Condition Symbol Min Typ Max Unit TX_CLK, GTX_CLK clock period tFIT 5.3 8.0 100 ns TX_CLK, GTX_CLK duty cycle tFITH/tFIT 45 50 55 % TX_CLK, GTX_CLK peak-to-peak jitter tFITJ —— 250 ps Rise time TX_CLK (20%–80%) tFITR — — 0.75 ns Fall time TX_CLK (80%–20%) tFITF — — 0.75 ns FIFO data TXD[7:0], TX_ER, TX_EN setup time to GTX_CLK tFITDV 2.0 — — ns GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold time tFITDX 0.5 — 3.0 ns Table 25. FIFO Mode Receive AC Timing Specification Parameter/Condition Symbol Min Typ Max Unit RX_CLK clock period tFIR 5.3 8.0 100 ns RX_CLK duty cycle tFIRH/tFIR 45 50 55 % RX_CLK peak-to-peak jitter tFIRJ —— 250 ps Rise time RX_CLK (20%–80%) tFIRR — — 0.75 ns Fall time RX_CLK (80%–20%) tFIRF — — 0.75 ns RXD[7:0], RX_DV, RX_ER setup time to RX_CLK tFIRDV 1.5 — — ns RXD[7:0], RX_DV, RX_ER hold time to RX_CLK tFIRDX 0.5 — — ns Note: 1. The minimum cycle period of the TX_CLK and RX_CLK is dependent on the maximum platform frequency of t he speed bins the part belongs to as well as the FIFO mode under operation. See Section 4.5, “Platform to FIFO Restrictions.” tFIT tFITH tFITF TXD[7:0] TX_EN GTX_CLK TX_ER tFITR tFITDV tFITDX |
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