MPC8548ECPXATHC datasheet(20/151 Pages) FREESCALE

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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9

Freescale Semiconductor

DDR and DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the

device. Note that GVDD(typ) = 2.5 V for DDR SDRAM, and GVDD(typ) = 1.8 V for DDR2 SDRAM.

6.1

DDR SDRAM DC Electrical Characteristics

The following table provides the recommended operating conditions for the DDR2 SDRAM controller of

the device when GVDD(typ) = 1.8 V.

This table provides the DDR2 I/O capacitance when GVDD(typ) = 1.8 V.

Table 11. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V

Parameter/Condition

Symbol

Min

Max

Unit

Notes

I/O supply voltage

GVDD

1.71

1.89

I/O reference voltage

MVREF

0.49

 GV

0.51

 GV

I/O termination voltage

VTT

MVREF –0.04

MVREF + 0.04

Input high voltage

VIH

MVREF +0.125

GVDD +0.3

—

Input low voltage

VIL

–0.3

MVREF –0.125

—

Output leakage current

IOZ

–50

A4

Output high current (VOUT = 1.420 V)

IOH

–13.4

—

Output low current (VOUT = 0.280 V)

IOL

13.4

—

Notes:

1. GVDD is expected to be within 50 mV of the DRAM VDD at all times.

2. MVREF is expected to be equal to 0.5  GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak

noise on MVREF may not exceed ±2% of the DC value.

3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MVREF. This rail must track variations in the DC level of MVREF.

4. Output leakage is measured with all outputs disabled, 0 V

 V

OUT GVDD.

Table 12. DDR2 SDRAM Capacitance for GVDD(typ)=1.8 V

Parameter/Condition

Symbol

Min

Max

Unit

Notes

Input/output capacitance: DQ, DQS, DQS

CIO

Delta input/output capacitance: DQ, DQS, DQS

CDIO

—0.5

Note:

1. This parameter is sampled. GVDD = 1.8 V ± 0.090 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.

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