MPC8548ECPXATHC datasheet(11/151 Pages) FREESCALE

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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9

Freescale Semiconductor

Electrical Characteristics

2.1.2

Recommended Operating Conditions

The following table provides the recommended operating conditions for this device. Note that the values

in this table are the recommended and tested operating conditions. Proper device operation outside these

conditions is not guaranteed.

Storage temperature range

TSTG

–55 to 150

C—

Notes:

1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and

functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause

permanent damage to the device.

2. The –0.3 to 2.75 V range is for DDR and –0.3 to 1.98 V range is for DDR2.

3. The 3.63 V maximum is only supported when the port is configured in GMII, MII, RMII, or TBI modes; otherwise the 2.75 V

maximum applies. See Section 8.2, “FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications,” for details on

the recommended operating conditions per protocol.

4. (M,L,O)VIN may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.

Table 2. Recommended Operating Conditions

Characteristic

Symbol

Recommended

Value

Unit

Notes

Core supply voltage

VDD

1.1 V ± 55 mV

—

PLL supply voltage

AVDD

1.1 V ± 55 mV

Core power supply for SerDes transceivers

SVDD

1.1 V ± 55 mV

—

Pad power supply for SerDes transceivers

XVDD

1.1 V ± 55 mV

—

DDR and DDR2 DRAM I/O voltage

GVDD

2.5 V ± 125 mV

1.8 V ± 90 mV

V—

Three-speed Ethernet I/O voltage

LVDD

3.3 V ± 165 mV

2.5 V ± 125 mV

TVDD

3.3 V ± 165 mV

2.5 V ± 125 mV

—

PCI/PCI-X, DUART, system control and power management, I2C,

Ethernet MII management, and JTAG I/O voltage

OVDD

3.3 V ± 165 mV

Local bus I/O voltage

BVDD

3.3 V ± 165 mV

2.5 V ± 125 mV

V—

Input voltage

DDR and DDR2 DRAM signals

MVIN

GND to GVDD

DDR and DDR2 DRAM reference

MVREF

GND to GVDD/2

Three-speed Ethernet signals

LVIN

TVIN

GND to LVDD

GND to TVDD

Local bus signals

BVIN

GND to BVDD

V—

PCI, DUART, SYSCLK, system control and power

management, I2C, Ethernet MII management, and

JTAG signals

OVIN

GND to OVDD

Table 1. Absolute Maximum Ratings 1 (continued)

Characteristic

Symbol

Max Value

Unit

Notes

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