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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M68ICS08GR датащи(PDF) 185 Page - Freescale Semiconductor, Inc |
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M68ICS08GR датащи(HTML) 185 Page - Freescale Semiconductor, Inc |
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185 / 408 page  Low-Voltage Inhibit (LVI) Functional Description MC68HC908GR8 — Rev 4.0 Technical Data MOTOROLA Low-Voltage Inhibit (LVI) 185 LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the configuration register (MOR1). See Configuration Register (CONFIG) for details of the LVI’s configuration bits. Once an LVI reset occurs, the MCU remains in reset until VDD rises above a voltage, VTRIPR, which causes the MCU to exit reset. See Low-Voltage Inhibit (LVI) Reset for details of the interaction between the SIM and the LVI. The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR). An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices. Figure 14-1. LVI Module Block Diagram LOW VDD DETECTOR LVIPWRD STOP INSTRUCTION LVISTOP LVI RESET LVIOUT VDD > LVITrip = 0 VDD ≤ LVITrip = 1 FROM CONFIG FROM CONFIG VDD FROM CONFIG LVIRSTD LVI5OR3 FROM CONFIG Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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