PIC16F87 datasheet(112/230 Pages) MICROCHIP

112 / 230 page

PIC16F87/88

DS30487D-page 112

 2002-2013 Microchip Technology Inc.

11.4.2

AUSART SYNCHRONOUS SLAVE

RECEPTION

The operation of the Synchronous Master and Slave

modes is identical, except in the case of the Sleep

mode. Bit SREN is a “don’t care” in Slave mode.

If receive is enabled by setting bit CREN prior to the

SLEEP

instruction, then a word may be received during

Sleep. On completely receiving the word, the RSR reg-

ister will transfer the data to the RCREG register and if

enable bit RCIE bit is set, the interrupt generated will

wake the chip from Sleep. If the global interrupt is

enabled, the program will branch to the interrupt vector

(0004h).

When setting up a synchronous slave reception, follow

these steps:

Enable the synchronous master serial port by

setting bits SYNC and SPEN and clearing bit

CSRC.

If interrupts are desired, set enable bit RCIE.

If 9-bit reception is desired, set bit RX9.

To enable reception, set enable bit CREN.

Flag bit RCIF will be set when reception is

complete and an interrupt will be generated if

enable bit RCIE was set.

Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

Read the 8-bit received data by reading the

RCREG register.

If any error occurred, clear the error by clearing

bit CREN.

If using interrupts, ensure that GIE and PEIE

(bits 7 and 6) of the INTCON register are set.

TABLE 11-13: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR, BOR

Value on

all other

Resets

0Bh, 8Bh,

10Bh,18Bh

INTCON

GIE

PEIE

TMR0IE INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 000x

0000 000u

0Ch

PIR1

—

ADIF(1)

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

-000 0000 -000 0000

18h

RCSTA

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

0000 000x 0000 000x

1Ah

RCREG

AUSART Receive Data Register

0000 0000 0000 0000

8Ch

PIE1

—

ADIE(1)

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE -000 0000 -000 0000

98h

TXSTA

CSRC

TX9

TXEN

SYNC

—

BRGH

TRMT

TX9D

0000 -010 0000 -010

99h

SPBRG

Baud Rate Generator Register

0000 0000 0000 0000

Legend:

= unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.

Note

This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87.

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