PIC16F87 datasheet(111/230 Pages) MICROCHIP

111 / 230 page

 2002-2013 Microchip Technology Inc.

DS30487D-page 111

PIC16F87/88

FIGURE 11-11:

SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

11.4

AUSART Synchronous Slave Mode

Synchronous Slave mode differs from the Master mode

in the fact that the shift clock is supplied externally at

the RB5/SS/TX/CK pin (instead of being supplied inter-

nally in Master mode). This allows the device to trans-

fer or receive data while in Sleep mode. Slave mode is

entered by clearing bit CSRC (TXSTA<7>).

11.4.1

AUSART SYNCHRONOUS SLAVE

TRANSMIT

The operation of the Synchronous Master and Slave

modes is identical, except in the case of the Sleep mode.

If two words are written to the TXREG and then the

SLEEP

instruction is executed, the following will occur:

The first word will immediately transfer to the

TSR register and transmit.

The second word will remain in the TXREG register.

Flag bit TXIF will not be set.

When the first word has been shifted out of TSR,

the TXREG register will transfer the second word

to the TSR and flag bit TXIF will now be set.

If enable bit TXIE is set, the interrupt will wake

the chip from Sleep and if the global interrupt is

enabled, the program will branch to the interrupt

vector (0004h).

When setting up a synchronous slave transmission,

follow these steps:

Enable the synchronous slave serial port by

setting bits SYNC and SPEN and clearing bit

CSRC.

Clear bits CREN and SREN.

If interrupts are desired, then set enable bit

TXIE.

If 9-bit transmission is desired, then set bit TX9.

Enable the transmission by setting enable bit

TXEN.

If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

Start transmission by loading data to the TXREG

If using interrupts, ensure that GIE and PEIE

(bits 7 and 6) of the INTCON register are set.

TABLE 11-12: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

CREN bit

RB2/SDO/RX/DT

RB5/SS/TX/CK

Write to

bit SREN

SREN bit

RCIF bit

(Interrupt)

Read

RXREG

Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0.

Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

‘0’

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

‘0’

Q1 Q2 Q3 Q4

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR, BOR

Value on

all other

Resets

0Bh, 8Bh,

10Bh,18Bh

INTCON

GIE

PEIE

TMR0IE INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 000x

0000 000u

0Ch

PIR1

—

ADIF(1)

RCIF

TXIF

SSPIF

CCP1IF TMR2IF TMR1IF -000 0000 -000 0000

18h

RCSTA

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

0000 000x

19h

TXREG

AUSART Transmit Data Register

0000 0000

8Ch

PIE1

—

ADIE(1)

RCIE

TXIE

SSPIE

CCP1IE TMR2IE TMR1IE -000 0000 -000 0000

98h

TXSTA

CSRC

TX9

TXEN

SYNC

—

BRGH

TRMT

TX9D

0000 -010

99h

SPBRG

Baud Rate Generator Register

0000 0000

Legend:

= unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.

Note

This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87.

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