PIC16F87 datasheet(116/230 Pages) MICROCHIP

116 / 230 page

PIC16F87/88

DS30487D-page 116

 2002-2013 Microchip Technology Inc.

The ADRESH:ADRESL registers contain the result of

the A/D conversion. When the A/D conversion is

complete, the result is loaded into the A/D Result register

pair, the GO/DONE bit (ADCON0<2>) is cleared and

A/D Interrupt Flag bit, ADIF, is set. The block diagram of

the A/D module is shown in Figure 12-1.

After the A/D module has been configured as desired,

the selected channel must be acquired before the

conversion is started. The analog input channels must

have their corresponding TRIS bits selected as inputs.

To determine sample time, see Section 12.1 “A/D

Acquisition Requirements”. After this sample time

has elapsed, the A/D conversion can be started.

These steps should be followed for doing an A/D

conversion:

Configure the A/D module:

• Configure analog/digital I/O (ANSEL)

• Configure voltage reference (ADCON1)

• Select A/D input channel (ADCON0)

• Select A/D conversion clock (ADCON0)

• Turn on A/D module (ADCON0)

Configure A/D interrupt (if desired):

• Clear ADIF bit

• Set ADIE bit

• SET PEIE bit

• Set GIE bit

Wait the required acquisition time.

Start conversion:

• Set GO/DONE bit (ADCON0)

Wait for A/D conversion to complete, by either:

• Polling for the GO/DONE bit to be cleared

(with interrupts disabled); OR

• Waiting for the A/D interrupt

Read A/D Result register pair

(ADRESH:ADRESL), clear bit ADIF if required.

For next conversion, go to step 1 or step 2 as

required. The A/D conversion time per bit is

defined as TAD. A minimum wait of 2 TAD is

required before the next acquisition starts.

FIGURE 12-1:

A/D BLOCK DIAGRAM

(Input Voltage)

VIN

VREF+

(Reference

Voltage)

AVDD

VCFG1:VCFG0

CHS2:CHS0

RA3/AN3/VREF+/C1OUT

RA2/AN2/CVREF/VREF-

RA1/AN1

RA0/AN0

011

010

001

000

A/D

Converter

VREF-

(Reference

Voltage)

AVSS

VCFG1:VCFG0

RB6/AN5/PGC/T1OSO/T1CKI

RB7/AN6/PGD/T1OSI

RA4/AN4/T0CKI/C2OUT

110

101

100

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