PIC16F87 datasheet(87/230 Pages) MICROCHIP

87 / 230 page

 2002-2013 Microchip Technology Inc.

DS30487D-page 87

PIC16F87/88

10.0

SYNCHRONOUS SERIAL PORT

(SSP) MODULE

10.1

SSP Module Overview

The Synchronous Serial Port (SSP) module is a serial

interface useful for communicating with other periph-

eral or microcontroller devices. These peripheral

devices may be serial EEPROMs, shift registers,

display drivers, A/D converters, etc. The SSP module

can operate in one of two modes:

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I2C™)

An overview of I2C operations and additional informa-

tion on the SSP module can be found in the “PIC® Mid-

Range MCU Family Reference Manual” (DS33023).

Refer to Application Note AN578, “Use of the SSP

Module in the I 2C™ Multi-Master Environment”

(DS00578).

10.2

SPI Mode

This

section

contains

definitions

and

operational characteristics of the SPI module.

SPI mode allows 8 bits of data to be synchronously

transmitted

and

received

simultaneously.

accomplish communication, typically three pins are

used:

• Serial Data Out (SDO)

RB2/SDO/RX/DT

• Serial Data In (SDI)

RB1/SDI/SDA

• Serial Clock (SCK)

RB4/SCK/SCL

Additionally, a fourth pin may be used when in a Slave

mode of operation:

• Slave Select (SS)

RB5/SS/TX/CK

When initializing the SPI, several options need to be

specified. This is done by programming the appropriate

control bits in the SSPCON register (SSPCON<5:0>)

and the SSPSTAT register (SSPSTAT<7:6>). These

control bits allow the following to be specified:

• Master mode (SCK is the clock output)

• Slave mode (SCK is the clock input)

• Clock Polarity (Idle state of SCK)

• Clock Edge (output data on rising/falling

edge of SCK)

• Clock Rate (Master mode only)

• Slave Select mode (Slave mode only)

Note:

Before enabling the module in SPI Slave

mode, the state of the clock line (SCK)

must match the polarity selected for the

Idle state. The clock line can be observed

by reading the SCK pin. The polarity of the

Idle state is determined by the CKP bit

(SSPCON<4>).

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