PIC16F87 datasheet(29/230 Pages) MICROCHIP

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 2002-2013 Microchip Technology Inc.

DS30487D-page 29

PIC16F87/88

3.3

Reading Data EEPROM Memory

To read a data memory location, the user must write the

address to the EEADR register, clear the EEPGD con-

trol bit (EECON1<7>) and then set control bit RD

(EECON1<0>). The data is available in the very next

cycle in the EEDATA register; therefore, it can be read

in the next instruction (see Example 3-1). EEDATA will

hold this value until another read or until it is written to

by the user (during a write operation).

The steps to reading the EEPROM data memory are:

Write the address to EEADR. Make sure that the

address is not larger than the memory size of

the device.

Clear the EEPGD bit to point to EEPROM data

memory.

Set the RD bit to start the read operation.

Read the data from the EEDATA register.

EXAMPLE 3-1:

DATA EEPROM READ

3.4

Writing to Data EEPROM Memory

To write an EEPROM data location, the user must first

write the address to the EEADR register and the data to

the EEDATA register. Then, the user must follow a

specific write sequence to initiate the write for each byte.

The write will not initiate if the write sequence is not

exactly followed (write 55h to EECON2, write AAh to

EECON2, then set WR bit) for each byte. We strongly

recommend that interrupts be disabled during this

code segment (see Example 3-2).

Additionally, the WREN bit in EECON1 must be set to

enable write. This mechanism prevents accidental

writes to data EEPROM due to errant (unexpected)

code execution (i.e., lost programs). The user should

keep the WREN bit clear at all times except when

updating EEPROM. The WREN bit is not cleared

by hardware

After a write sequence has been initiated, clearing the

WREN bit will not affect this write cycle. The WR bit will

be inhibited from being set unless the WREN bit is set.

At the completion of the write cycle, the WR bit is

cleared in hardware and the EE Write Complete

Interrupt Flag bit (EEIF) is set. The user can either

enable this interrupt or poll this bit. EEIF must be

cleared by software.

The steps to write to EEPROM data memory are:

If step 10 is not implemented, check the WR bit

to see if a write is in progress.

Write the address to EEADR. Make sure that the

address is not larger than the memory size of

the device.

Write the 8-bit data value to be programmed in

the EEDATA register.

Clear the EEPGD bit to point to EEPROM data

memory.

Set the WREN bit to enable program operations.

Disable interrupts (if enabled).

Execute the special five instruction sequence:

Write 55h to EECON2 in two steps (first to W,

then to EECON2).

Write AAh to EECON2 in two steps (first to W,

then to EECON2).

Set the WR bit.

Enable interrupts (if using interrupts).

Clear the WREN bit to disable program

operations.

10. At the completion of the write cycle, the WR bit

is cleared and the EEIF interrupt flag bit is set

(EEIF must be cleared by firmware). If step 1 is

not implemented, then firmware should check

for EEIF to be set, or WR to clear, to indicate the

end of the program cycle.

EXAMPLE 3-2:

DATA EEPROM WRITE

BANKSEL EEADR

; Select Bank of EEADR

MOVF

ADDR, W

;

MOVWF

EEADR

; Data Memory Address

; to read

BANKSEL EECON1

; Select Bank of EECON1

BCF

EECON1, EEPGD; Point to Data memory

BSF

EECON1, RD

; EE Read

BANKSEL EEDATA

; Select Bank of EEDATA

MOVF

EEDATA, W

; W = EEDATA

BANKSEL EECON1

; Select Bank of

; EECON1

BTFSC

EECON1, WR

; Wait for write

GOTO

$-1

; to complete

BANKSEL EEADR

; Select Bank of

; EEADR

MOVF

ADDR, W

;

MOVWF

EEADR

; Data Memory

; Address to write

MOVF

VALUE, W

;

MOVWF

EEDATA

; Data Memory Value

; to write

BANKSEL EECON1

; Select Bank of

; EECON1

BCF

EECON1, EEPGD ; Point to DATA

; memory

BSF

EECON1, WREN

; Enable writes

BCF

INTCON, GIE

; Disable INTs.

MOVLW

55h

;

MOVWF

EECON2

; Write 55h

MOVLW

AAh

;

MOVWF

EECON2

; Write AAh

BSF

EECON1, WR

; Set WR bit to

; begin write

BSF

INTCON, GIE

; Enable INTs.

BCF

EECON1, WREN

; Disable writes

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