PIC16F87 datasheet(45/230 Pages) MICROCHIP

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DS30487D-page 45

PIC16F87/88

4.7.3

SEC_RUN/RC_RUN TO PRIMARY

CLOCK SOURCE

When switching from a SEC_RUN or RC_RUN mode

back to the primary system clock, following a change

of SCS<1:0> to ‘00’, the sequence of events that takes

place will depend upon the value of the FOSC bits in

the Configuration register. If the primary clock source

is configured as a crystal (HS, XT or LP), then the tran-

sition will take place after 1024 clock cycles. This is

necessary because the crystal oscillator has been

powered down until the time of the transition. In order

to provide the system with a reliable clock when the

changeover has occurred, the clock will not be

released to the changeover circuit until the 1024 count

has expired.

During the oscillator start-up time, the system clock

comes from the current system clock. Instruction

execution and/or peripheral operation continues using

the currently selected oscillator as the CPU clock

source, until the necessary clock count has expired, to

ensure that the primary system clock is stable.

To know when the OST has expired, the OSTS bit

should be monitored. OSTS = 1 indicates that the

Oscillator Start-up Timer has timed out and the system

clock comes from the primary clock source.

Following the oscillator start-up time, the internal Q

clocks are held in the Q1 state until eight falling edge

clocks are counted from the primary system clock. The

clock input to the Q clocks is then released and opera-

tion resumes with the primary system clock determined

by the FOSC bits (see Figure 4-10).

When in SEC_RUN mode, the act of clearing the

T1OSCEN bit in the T1CON register will cause

SCS<0> to be cleared, which causes the SCS<1:0>

bits to revert to ‘00’ or ‘10’ depending on what SCS<1>

is. Although the T1OSCEN bit was cleared, T1OSC will

be enabled and instruction execution will continue until

the OST time-out for the main system clock is com-

plete. At that time, the system clock will switch from the

T1OSC to the primary clock or the INTRC. Following

this, the T1 oscillator will be shut down.

4.7.3.1

Returning to Primary Clock Source

Sequence

Changing

back

the

primary

oscillator

from

SEC_RUN or RC_RUN can be accomplished by either

changing SCS<1:0> to ‘00’, or clearing the T1OSCEN

bit in the T1CON register (if T1OSC was the secondary

clock).

The sequence of events that follows is the same for

both modes:

If the primary system clock is configured as EC,

RC or INTRC, then the OST time-out is skipped.

Skip to step 3.

If the primary system clock is configured as an

external oscillator (HS, XT, LP), then the OST

will be active, waiting for 1024 clocks of the

primary system clock.

On the following Q1, the device holds the

system clock in Q1.

The device stays in Q1 while eight falling edges

of the primary system clock are counted.

Once the eight counts transpire, the device

begins to run from the primary oscillator.

If the secondary clock was INTRC and the

primary is not INTRC, the INTRC will be shut

down to save current providing that the INTRC

is not being used for any other function, such as

WDT or Fail-Safe Clock monitoring.

If the secondary clock was T1OSC, the T1OSC

will continue to run if T1OSCEN is still set;

otherwise, the T1 oscillator will be shut down.

Note:

If the primary system clock is either RC or

EC, an internal delay timer (5-10

s) will

suspend operation after exiting Secondary

Clock mode to allow the CPU to become

ready for code execution.

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